SLOS187A February   1997  – July 2025 TLV2322 , TLV2324

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Dissipation Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Electrical Characteristics, TLV2322
    5. 5.5  Operating Characteristics TLV2322, VDD = 3V
    6. 5.6  Operating Characteristics, TLV2322, VDD = 5V
    7. 5.7  Electrical Characteristics, TLV2324
    8. 5.8  Operating Characteristics, TLV2324, VDD = 3V
    9. 5.9  Operating Characteristics, TLV2324, VDD = 5V
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Single-Supply Versus Split-Supply Test Circuits
    2. 6.2 Input Bias Current
    3. 6.3 Low-level Output Voltage
    4. 6.4 Input Offset Voltage Temperature Coefficient
    5. 6.5 Full-Power Response
    6. 6.6 Test Time
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Single-Supply Operation
      2. 7.1.2 Input Characteristics
      3. 7.1.3 Noise Performance
      4. 7.1.4 Feedback
      5. 7.1.5 Electrostatic-Discharge Protection
      6. 7.1.6 Latch-Up
      7. 7.1.7 Output Characteristics
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.1.2 Input Characteristics

The TLV232x is specified with a minimum and a maximum input voltage that if exceeded at either input, possibly causes the device to malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. The lower range limit includes the negative rail, while the upper range limit is specified at VDD – 1V at TA = 25°C and at VDD – 1.2V at all other temperatures.

The use of the polysilicon-gate process and the careful input circuit design gives the legacy TLV232x very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time is calculated to be typically 0.1µV/month, including the first month of operation.

Migration from the legacy 150mm LinCMOS process to a 300mm diameter wafer process has brought associated improvements to input offset voltage precision, slew rate, phase margin, output current drive capability, and high-level output voltage. However, this change does introduce a new crossover region, where shifts in input offset (typically 300µV–400µV) occur as the input common-mode voltage approaches the VDD rail. Figure 7-2 and Figure 7-3 plot the mean and standard deviation of this characteristic at various temperatures for a 5V supply.

TLV2322 TLV2324 Offset Voltage vs Input Common-mode VoltageFigure 7-2 Offset Voltage vs Input Common-mode Voltage
TLV2322 TLV2324 Offset Voltage vs Input Common-mode VoltageFigure 7-3 Offset Voltage vs Input Common-mode Voltage

Because of the extremely high input impedance and resulting low bias-current requirements, the TLV232x is an excellent choice for low-level signal processing. However, leakage currents on printed-circuit boards and sockets sometimes easily exceed bias-current requirements and cause a degradation in device performance. As best practice, include guard rings around inputs (similar to those of Figure 6-4 in the Parameter Measurement Information section). Drive these guards from a low-impedance source at the same voltage level as the common-mode input (see Figure 7-4).

Tie the inputs of any unused amplifiers to ground to avoid possible oscillation.

TLV2322 TLV2324 Guard-Ring Schemes Figure 7-4 Guard-Ring Schemes