SLOS187A February   1997  – July 2025 TLV2322 , TLV2324

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Dissipation Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Electrical Characteristics, TLV2322
    5. 5.5  Operating Characteristics TLV2322, VDD = 3V
    6. 5.6  Operating Characteristics, TLV2322, VDD = 5V
    7. 5.7  Electrical Characteristics, TLV2324
    8. 5.8  Operating Characteristics, TLV2324, VDD = 3V
    9. 5.9  Operating Characteristics, TLV2324, VDD = 5V
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Single-Supply Versus Split-Supply Test Circuits
    2. 6.2 Input Bias Current
    3. 6.3 Low-level Output Voltage
    4. 6.4 Input Offset Voltage Temperature Coefficient
    5. 6.5 Full-Power Response
    6. 6.6 Test Time
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Single-Supply Operation
      2. 7.1.2 Input Characteristics
      3. 7.1.3 Noise Performance
      4. 7.1.4 Feedback
      5. 7.1.5 Electrostatic-Discharge Protection
      6. 7.1.6 Latch-Up
      7. 7.1.7 Output Characteristics
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TLV2322 TLV2324 TLV2322 D Package, 8-Pin SOIC and P Package, 8-Pin PDIP (Top View)Figure 4-1 TLV2322 D Package, 8-Pin SOIC and P Package, 8-Pin PDIP (Top View)
TLV2322 TLV2324 TLV2322 PW Package, 8-Pin TSSOP (Top View)Figure 4-2 TLV2322 PW Package, 8-Pin TSSOP (Top View)
Table 4-1 Pin Functions: TLC2322
PIN TYPE DESCRIPTION
NAME NO.
1IN+ 3 Input Noninverting input, channel 1
1IN– 2 Input Inverting input, channel 1
2IN+ 5 Input Noninverting input, channel 2
2IN– 6 Input Inverting input, channel 2
OUT1 1 Output Output, channel 1
OUT2 7 Output Output, channel 2
VDD+ 8 — Positive (highest) power supply
VDD– / GND 4 — Ground or negative (lowest) power supply
TLV2322 TLV2324 TLV2324 D Package, 14-Pin SOIC, or N Package, 14-Pin PDIP (Top View)Figure 4-3 TLV2324 D Package, 14-Pin SOIC, or N Package, 14-Pin PDIP (Top View)
TLV2322 TLV2324 TLV2324 PW Package, 14-Pin TSSOP (Top View)Figure 4-4 TLV2324 PW Package, 14-Pin TSSOP (Top View)
Table 4-2 Pin Functions: TLC2324
PIN TYPE DESCRIPTION
NAME NO.
1IN+ 3 Input Noninverting input, channel 1
1IN– 2 Input Inverting input, channel 1
2IN+ 5 Input Noninverting input, channel 2
2IN– 6 Input Inverting input, channel 2
3IN+ 10 Input Noninverting input, channel 3
3IN– 9 Input Inverting input, channel 3
4IN+ 12 Input Noninverting input, channel 4
4IN– 13 Input Inverting input, channel 4
OUT1 1 Output Output, channel 1
OUT2 7 Output Output, channel 2
OUT3 8 Output Output, channel 3
OUT4 14 Output Output, channel 4
VDD+ 4 — Positive (highest) power supply
VDD– / GND 11 — Ground or negative (lowest) power supply