SLUS812E February   2008  – September 2025 TPS51200

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Sink and Source Regulator (VO Pin)
      2. 6.3.2  Reference Input (REFIN Pin)
      3. 6.3.3  Reference Output (REFOUT Pin)
      4. 6.3.4  Soft-Start Sequencing
      5. 6.3.5  Enable Control (EN Pin)
      6. 6.3.6  Powergood Function (PGOOD Pin)
      7. 6.3.7  Current Protection (VO Pin)
      8. 6.3.8  UVLO Protection (VIN Pin)
      9. 6.3.9  Thermal Shutdown
      10. 6.3.10 Tracking Start-up and Shutdown
      11. 6.3.11 Output Tolerance Consideration for VTT DIMM Applications
      12. 6.3.12 REFOUT (VREF) Consideration for DDR2 Applications
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Input Voltage Applications
      2. 6.4.2 S3 and Pseudo-S5 Support
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Voltage Capacitor
        2. 7.2.2.2 VLDO Input Capacitor
        3. 7.2.2.3 Output Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 System Examples
      1. 7.3.1 3.3VIN, DDR2 Configuration
      2. 7.3.2 2.5VIN, DDR3 Configuration
      3. 7.3.3 3.3VIN, LP DDR3 or DDR4 Configuration
      4. 7.3.4 3.3VIN, DDR3 Tracking Configuration
      5. 7.3.5 3.3VIN, LDO Configuration
      6. 7.3.6 3.3VIN, DDR3 Configuration with LFP
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
      3. 7.5.3 Thermal Design Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4.2 S3 and Pseudo-S5 Support

The TPS51200 provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal in the end application. Both REFOUT and VO are on when EN = high (S0 state). REFOUT is maintained while VO is turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). When EN = low and the REFIN voltage is less than 0.390V, TPS51200 enters pseudo-S5 state. Both VO and REFOUT outputs are turned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged (S4 or S5 state). Figure 6-1 shows a typical start-up and shutdown timing diagram for an application that uses S3 and pseudo-S5 support.