SLUSF91 December   2025 UCC23710

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power Supplies
      2. 6.3.2  VDD Undervoltage Lockout (UVLO)
      3. 6.3.3  Opto-Emulated Input
      4. 6.3.4  Driver Stage
      5. 6.3.5  Active Pulldown
      6. 6.3.6  Short Circuit Clamping
      7. 6.3.7  Internal Active Miller Clamp
      8. 6.3.8  Desaturation (DESAT) Protection
      9. 6.3.9  Soft Turn Off (STO)
      10. 6.3.10 Fault (FLT) and Reset
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selecting the Input Resistor
        2. 7.2.2.2 Gate Driver Output Resistor
        3. 7.2.2.3 FLT Output
        4. 7.2.2.4 Estimate Gate-Driver Power Loss
        5. 7.2.2.5 Selecting VDD Capacitor
        6. 7.2.2.6 Overcurrent and Short Circuit Protection
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.4 Estimate Gate-Driver Power Loss

The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC23710 device and the power losses in the peripheral circuitry, such as the external gate-drive resistor.

The PGD value is the key power loss which determines the thermal safety-related limits of the UCC23710 device, and it can be estimated by calculating losses from several components.

The first component is the static power loss, PGDQ, which includes power dissipated in the input stage (PGDQ_IN) as well as the quiescent power dissipated in the output stage (PGDQ_OUT) when operating with a certain switching frequency under no load. PGDQ_IN is determined by IF and VF and is given by Equation 5. The PGDQ_OUT parameter is measured on the bench with no load connected to VOUT pin at a given VDD, switching frequency, and ambient temperature. In this example, VDD is 15V. The current on the power supply, with PWM switching at 10kHz, is measured to be IDD = 1.33mA . Therefore, use Equation 6 to calculate PGDQ_OUT.

Equation 5. PGDQIN=12×VF×IF
Equation 6. PGDQOUT=VDD×IDD

The total quiescent power (without any load capacitance) dissipated in the gate driver is given by the sum of Equation 5 and Equation 6 as shown in Equation 7.

Equation 7. PGDQ=PGDQIN+PGDQOUT=9mW+20mW=29mW

The second component is the switching operation loss, PGDSW, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Use Equation 8 to calculate the total dynamic loss from load switching, PGSW.

Equation 8. PGSW=VDD×QG×fSW

where

  • QG is the gate charge of the power transistor at VDD.

So, for this example application the total dynamic loss from load switching is approximately 18mW as calculated in Equation 9.

Equation 9. PGSW=15V×120nC×10kHz=18mW

QG represents the total gate charge of the power transistor switching 520V at 50A, and is subject to change with different testing conditions. The UCC23710 gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO is equal to PGSW if the external gate-driver resistance and power-transistor internal resistances are 0Ω, and all the gate driver-loss is dissipated inside the UCC23710. If an external turn-on and turn-off resistance exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and power-transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 5A/5A, however, it will be nonlinear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

Equation 10. PGDO=PGSW2ROHROH+RGON+RGFETint+ROLROL+RGON||RGOFF+RGFETint 

In this design example, all the predicted source and sink currents are less than 5A and 5A, therefore, use Equation 10 to estimate the UCC23525 gate-driver loss.

Equation 11. PGDO=18mW22.5Ω2.5Ω+10Ω+0Ω+0.7Ω0.7Ω+10Ω||10Ω+0Ω 

Case 2 - Nonlinear Pull-Up/Down Resistor:

Equation 12. PGDO=fsw×∫0TRSys5A×VDD-VOUTtdt+∫0TRSys5A×VOUTt dt

where

  • VOUT(t) is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is saturated for some time, this value can be simplified as a constant-current source (5A at turnon and 5A at turnoff) charging or discharging a load capacitor. Then, the VOUT(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.

For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the PGDO is a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based on this discussion.

Use Equation 13 to calculate the total gate-driver loss dissipated in the UCC23710 gate driver, PGD.

Equation 13. PGD=PGDQ+PGDO=29mW+2.9mW=31.9mW