SLUSF91 December   2025 UCC23710

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power Supplies
      2. 6.3.2  VDD Undervoltage Lockout (UVLO)
      3. 6.3.3  Opto-Emulated Input
      4. 6.3.4  Driver Stage
      5. 6.3.5  Active Pulldown
      6. 6.3.6  Short Circuit Clamping
      7. 6.3.7  Internal Active Miller Clamp
      8. 6.3.8  Desaturation (DESAT) Protection
      9. 6.3.9  Soft Turn Off (STO)
      10. 6.3.10 Fault (FLT) and Reset
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selecting the Input Resistor
        2. 7.2.2.2 Gate Driver Output Resistor
        3. 7.2.2.3 FLT Output
        4. 7.2.2.4 Estimate Gate-Driver Power Loss
        5. 7.2.2.5 Selecting VDD Capacitor
        6. 7.2.2.6 Overcurrent and Short Circuit Protection
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air > 8 mm
CPG External Creepage(1) Shortest terminal-to-terminal distance across the package surface > 8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) > 17 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material Group According to IEC 60664–1 I
Overvoltage Category per IEC 60664–1 Rated mains voltage ≤ 300 VRMS I-IV
Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN V VDE 0884-10 (VDE V 0884-10): 2016-12
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1500 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; see Figure 1 1060 VRMS
DC voltage 1500 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test)
VTEST= 1.2 × VIOTM, t = 1 s (100% production test)		 7071 VPK
VIMP Maximum inpulse voltage (2) Tested in air, 1.2/50-µs waveform per IEC 62368-1 7692 VPK
VIOSM Maximum surge isolation voltage (3) Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 11300 VPK (qualification) 10000 VPK
qpd Apparent charge (4) Method a: After I/O safety test subgroup 2/3, Vini =VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s ≤ 5 pC
Method a: After environmental tests subgroup 1,Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s ≤ 5
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = x VPK, tm = 1 s ≤ 5
CIO Barrier capacitance, input to output (5) VIO = 0.5 × sin (2πft), f = 1 MHz ~ 1 pF
RIO Insulation resistance, input to output (5) VIO = 500 V,  TA = 25°C ≥ 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 125°C ≥ 1011
VIO = 500 V at  TS = 150°C ≥ 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 5000 VRMS, t = 60 s (qualification), VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production) 5000 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) Testing is carried out in air to determine the surge immunity of the package.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.