SLUSF91 December   2025 UCC23710

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power Supplies
      2. 6.3.2  VDD Undervoltage Lockout (UVLO)
      3. 6.3.3  Opto-Emulated Input
      4. 6.3.4  Driver Stage
      5. 6.3.5  Active Pulldown
      6. 6.3.6  Short Circuit Clamping
      7. 6.3.7  Internal Active Miller Clamp
      8. 6.3.8  Desaturation (DESAT) Protection
      9. 6.3.9  Soft Turn Off (STO)
      10. 6.3.10 Fault (FLT) and Reset
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selecting the Input Resistor
        2. 7.2.2.2 Gate Driver Output Resistor
        3. 7.2.2.3 FLT Output
        4. 7.2.2.4 Estimate Gate-Driver Power Loss
        5. 7.2.2.5 Selecting VDD Capacitor
        6. 7.2.2.6 Overcurrent and Short Circuit Protection
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.9 Electrical Characteristics

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD - COM = 20 V, 18 V or 15V, COM - VEE = 0 V, 5 V, 8 V or 15V, CL = 100 pF, -40℃ < TJ < 150℃ (unless otherwise noted)(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT STAGE
IFLH Low to High Input Forward Current Threshold VDD-VEE = 15 V 1 2.7 mA
IF_HYS Input Forward Current Hysteresis VDD-VEE = 15 V 0.3 mA
VF Input Forward Voltage IF = 10 mA 1.4 1.7 2 V
ΔVF/ΔT Input Forward Voltage Temp. Coefficient   IF = 10 mA 0.7 mV/℃
VR Input Reverese Breakdown Voltage IR = 10 uA 6 V
CIN Input Capacitance fs = 0.5 MHz, +/- 250 mV 4 pF
POWER SUPPLY QUIESCENT CURRENT
IVCCQ VCC quiescent current OUT = High, fs = 0 Hz 1 2 mA
OUT = Low, fs = 0 Hz 1 2 mA
IVDDQ VDD quiescent current OUT = High, fs = 0 Hz 1 2.3
4

 mA
OUT = Low, fs = 0 Hz 1 2.0 3 mA
IVEEQ VEE quiescent current OUT = High, fs = 0 Hz, COM-VEE=5V -1.8 mA
OUT = Low, fs = 0 Hz, COM-VEE=5V -1.5 mA
POWER SUPPLY PROTECTION
VVDD_UVLO_ON VDD UVLO rising threshold VDD-COM 11.4 12 12.6 V
VVDD_UVLO_OFF VDD UVLO falling threshold VDD-COM 10.45 11 11.55 V
VVDD_HYST VDD UVLO hysteresis for 12V UVLO 1.1 V
tVDDFIL VDD UVLO deglitch time 5 µs
tVDD+ to OUT VDD UVLO on delay to output high IF(on) = 5mA 2 4.6 7 µs
tVDD- to OUT VDD UVLO on delay to output low 5.4 8.5 µs
GATE DRIVER STAGE
IOUT Peak source current CL = 0.22µF, fS = 1kHz 5 A
IOUT Peak sink current CL = 0.22µF, fS = 1kHz 5 A
ROUTH Output pull-up resistance IOH = 1A, CL=220nF, Fsw = 1khz 0.7 Ω
ROUTL Output pull-down resistance IOL = -1A, CL=220nF, Fsw = 1khz 0.7 Ω
ACTIVE PULLDOWN
VOUTPD Output active pull down on OUT IOUT = 0.1×IOUT(typ),
VDD=OPEN, VEE=COM		 1.4 2.0 2.5 V
INTERNAL MILLER CLAMP
VCLMPTH Miller clamp threshold voltage Reference to VEE 1.5 2.1 2.5 V
VCLMPI Output low clamp voltage ICLMPI = 20 mA   16   mV
ICLMPI Output low clamp current VCLMPI = 0V, VEE = –2.5V   2.3   A
RCLMPI Miller clamp pull down resistance ICLMPI = 0.2A   0.8   Ω
tDCLMPI Miller clamp ON delay time CL = 1.8nF   38 50 ns
SHORT CIRCUIT CLAMPING
VOUT_CLMP VOUT - VDD OUT = High, IOUT = 500mA, tCLP=10us 0.8 V
DESAT PROTECTION
ICHG Blanking capacitor charge current VDESAT = 2.0V 210 250 297 µA
IDCHG Blanking capacitor discharge current VDESAT = 6.0V (for VDESATTH > 6.5 )
VDESAT = 5.0V (for VDESATTH = 6.5 )		 25 40 mA
VDESATTH Detection threshold 8.4 9 9.6 V
tDESATLEB Leading edge blank time 320 470 540 ns
tDESATFIL DESAT deglitch filter 100 180 260 ns
tDESATOFF DESAT propagation delay to OUT 90% VDESAT>VDESATTH 200 ns
tDESATFLT DESAT to FLT low delay 260 ns
SOFT TURN OFF
ISTO Internal Soft Turn Off Current VOUT=8V, CL = 0.18µF, fS = 1kHz,  0.25 A
FAULT REPORTING (FLT)
tFLT_RST Fault flag clear time after device reset  From IF rising to Fault clearing 60 ns
tFLTMUTE Output mute time on overcurrent fault 22 us
RODON Open drain output on resistance IODON = 5mA 8.8 Ω
VFLT_OD Open drain low output voltage 0.15xVCC V
COMMON MODE TRANSIENT IMMUNITY
CMTI Common-mode Transient Immunity(3) VCM = 1200 V 300   V/ns
(1) Currents are positive into and negative out of the specified terminal.
(2) All voltages are referenced to COM unless otherwise noted
(3) For best CMTI performance, it is recommended to use a single resistor to the Anode pin, and connecting Cathode pin directly to GND.