SLUSG46 March   2026 BQ25785

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2578X
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi-dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  System Voltage Maximum Regulation (SYS_MAX)
        6. 7.3.26.6  Battery Overvoltage Protection (BATOVP)
        7. 7.3.26.7  Battery Charge Overcurrent Protection (BATCOC)
        8. 7.3.26.8  Battery Discharge Overcurrent Protection (BATDOC)
        9. 7.3.26.9  BATFET Charge Current Clamp Protection Under LDO Regulation Mode
        10. 7.3.26.10 Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 SMBus Interface
        1. 7.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 7.5.1.2 Timing Diagrams
    6. 7.6 BQ25785 Register Map
    7. 7.7 BQ25785 Registers
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Layout Example Reference Top View
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Processor Hot Indication

When CPU is running in turbo mode, the system peak power can exceed available power from adapter and battery together. The adapter current and battery discharge peak current, or system voltage drop is an indication that system power is too high. The charger processor hot function monitors these events, and PROCHOT pulse is asserted if the system power is too high. Once the CPU receives the PROCHOT pulse from the charger, the CPU slows down to reduce system power. The events monitored by the processor hot function include:

  • ICRIT: adapter peak current, as 110% of ILIM2
  • INOM: adapter average current (110% of IIN_DPM)
  • IDCHG1: battery discharge current level 1
  • IDCHG2: battery discharge current level 2. Note that IDCHG2 threshold is always larger than IDCHG1 threshold, determined by IDCHG_TH2 register setting.
  • VBUS_VAP: VBUS threshold to trigger PROCHOT in VAP mode
  • VSYS: system voltage on VSYS.
  • Adapter Removal: (When the adapter is removed, the prochot pin PROCHOT activates a single falling edge trigger when the VBUS falls below VVBUS_CONVENZ and deglitch time is within 1μs. If triggered, the STAT_ADAPTER_REMOVAL bit is set to 1b, the bit is high until clear through host read or REG_RESET bit. The status bit is level trigger which means if VBUS is still below VVBUS_CONVENZ when status bit gets cleared, then the status bit must be triggered again immediately)
  • Battery Removal: (When the battery is removed, the prochot pin PROCHOT activates a single falling edge trigger when CELL_BATPRES pin voltage falls below VCELL_BATPRES_FALL threshold and deglitch time is within 1μs. If triggered, the STAT_BATTERY_REMOVAL bit is set to 1b, the pin is locked until clear through host read or REG_RESET bit. The status bit is also falling edge trigger which means if CELL_BATPRES pin is still below VCELL_BATPRES_FALL when status bit gets cleared, the status bit is still cleared to 0b)
  • CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)
  • VINDPM: VBUS lower than 83%/91%/100% of VINDPM setting. The effective threshold PROCHOT_VINDPM is determined by combination of register PROCHOT_VINDPM_80_90 bit and LOWER_PROCHOT_VINDPM bit:
    • PROCHOT_VINDPM=VINDPM register setting: LOWER_PROCHOT_VINDPM=0b;
    • PROCHOT_VINDPM=83% VINDPM register setting: LOWER_PROCHOT_VINDPM=1b;PROCHOT_VINDPM_80_90=0b;
    • PROCHOT_VINDPM=91% VINDPM register setting: LOWER_PROCHOT_VINDPM=1b;PROCHOT_VINDPM_80_90=1b;
  • EXIT_VAP: Every time when the charger exits VAP mode.
  • THERMAL: If enabled (PP_THERMAL=1b), then when the CMPIN_TR pin voltage is lower than VTREG_PP for 1s/100ms (THERMAL_DEG bit configurable) deglitch time. Then STAT_THERMAL is latched until clear through a host read or REG_RESET bit.

The thresholds of ICRIT, IDCHG1,IDCHG2,VSYS or VINDPM, and the deglitch times of ICRIT, INOM, IDCHG1, IDCHG2, or CMPOUT are programmable. Except for the PROCHOT_EXIT_VAP which is always enabled, the other triggering events can be individually enabled in ProchotOption1[7:0], PP_IDCHG2 and PP_VBUS_VAP. When any enabled event in PROCHOT profile is triggered, PROCHOT is asserted low for a single pulse with minimal width  programmable in PROCHOT_WIDTH register bits. At the end of the single pulse, if the PROCHOT event is still active, the pulse gets extended until the event is removed.

If the PROCHOT pulse extension mode is enabled by setting EN_PROCHOT_EXT= 1b, the PROCHOT pin is kept low until the host writes PROCHOT_CLEAR= 1b, even if the triggering event has been removed.

If the PROCHOT_VINDPM or PROCHOT_EXIT_VAP is triggered, the PROCHOT pin always stay low until the host clears the pin, regardless of whether the PROCHOT is in one pulse mode or in extended mode. To clear PROCHOT_VINDPM, the host needs to write a 0 to STAT_VINDPM. To clear PROCHOT_EXIT_VAP, the host needs to write a 0 to STAT_EXIT_VAP.

BQ25785 PROCHOT ProfileFigure 7-10 PROCHOT Profile