SLUSG46 March   2026 BQ25785

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2578X
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi-dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  System Voltage Maximum Regulation (SYS_MAX)
        6. 7.3.26.6  Battery Overvoltage Protection (BATOVP)
        7. 7.3.26.7  Battery Charge Overcurrent Protection (BATCOC)
        8. 7.3.26.8  Battery Discharge Overcurrent Protection (BATDOC)
        9. 7.3.26.9  BATFET Charge Current Clamp Protection Under LDO Regulation Mode
        10. 7.3.26.10 Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 SMBus Interface
        1. 7.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 7.5.1.2 Timing Diagrams
    6. 7.6 BQ25785 Register Map
    7. 7.7 BQ25785 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Layout Example Reference Top View
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.3 REGN Regulator (REGN LDO)

The REGN LDO regulator provides a regulated bias supply for the IC and external pull up. Additionally, REGN voltage is also used to drive the buck-boost switching FETs. The pull-up rail of CELL_BATPRES pin and ILIM_HIZ pin can be connected to REGN as well. When there is no valid external 5V voltage source available on the system then REGN LDO is powered from either the VBUS pin or VSYS pin. The REGN power selector selects the lower of VBUS and VSYS if both are greater than 6V. The selector selects the higher of VBUS and VSYS if VBUS and VSYS are both lower than 6V and selects the one higher than 6V if there is only one higher than 6V. Both REGN_A and REGN_B pins are connected to REGN LDO internally, no external connections between REGN_A and REGN_B are needed, however 2.2µF local decoupling capacitance are needed for both REGN_A and REGN_B pins.

When there is a qualified 5V supply in the system, the supply can be leveraged as a REGN source. This can reduce power loss from the internal LDO, especially when both VBUS and VSYS are much higher than 5V. The LDO can be configured to be over-driven by external 5V source. Then REGN pin changes from an analog output pin to an analog input pin. REGN_EXT bit is used to configure in the following method.

  • When there is no qualified external 5V source, the host can configure REGN_EXT=0b (default status), then the internal REGN LDO regulation output voltage is 5V to normally support internal bias and switching MOSFET gate drive. There is an internal current limit to prevent LDO from over load. The current limit level is IREGN_LIM_CHARGING and is marked as current limit 1.
  • When there is dedicated qualified external 5V source(above 4.8V and below VREGN_OV_RISE) and REGN is the only load on external source, the host configures REGN_EXT=1b to reduce internal REGN LDO regulation output voltage to be VREGN_REG_EXT(4.5V), then external 5V regulator can over drive internal LDO. A maximum of 500mA current limit is needed for external power supply to prevent over current damaging on internal bootstrap diode. The application diagram is Figure 7-1.
  • When the external 5V source (above 4.8V and below VREGN_OV_RISE) is also supporting other loads besides REGN, a dedicated blocking circuit is needed to prevent REGN current from sourcing into external loads before external 5V buck converter ramp up shown in Figure 7-2. Before external 5V regulator power good (PG) is active, the QBLK serves to block external loading impact on REGN_A pin. After external 5V ramps up, external 5V regulation PG is active and QBLK is turned on to distribute 5V to REGN_A pin. The host configures REGN_EXT=1b to reduce internal REGN LDO regulation output voltage to be VREGN_REG_EXT(4.5V), then external 5V regulator can over drive to internal LDO automatically.
  • When the external 5V source is above VREGN_OV_RISE, the charger stops switching, pull down CHRG_OK pin, and trigger FAULT_REGN status bit. Refer also to Section 7.3.26.11.
BQ25785 External Dedicated 5V Source Over Drive REGN Figure 7-1 External Dedicated 5V Source Over Drive REGN
BQ25785 External 5V Source With Load Over Drive REGN Figure 7-2 External 5V Source With Load Over Drive REGN

The power dissipation for driving the gates via the REGN LDO is: PREGN = (VAC - VREGN) QG(TOT)*fSW, where QG(TOT) is the sum of the total gate charge for all practical switching FETs (1A,1B,2A,2B,3 and 4) and fSW is the programmed switching frequency.

Under the battery only condition, the following method can be used to flexibly configure REGN on and off:

  • When the charger is configured in low power mode(EN_LWPWR=1b), REGN by default is turned off (EN_REGN_LWPWR=0b). If the designer needs REGN voltage to supply circuit, the charger enables REGN by setting EN_REGN_LWPWR=1b. To save quiescent current under low power mode, the REGN current capability is scaled down to 5mA typical and 3mA minimum. When REGN receives host command to start up converter, like OTG or VAP mode is enabled, then REGN automatically recovers to full scale to support large gate drive current demand even with EN_LWPWR=1b.
  • When the charger is configured in performance mode (EN_LWPWR=0b), REGN is turned on with full scale capability neglecting EN_REGN_LWPWR configuration. This is needed to support OTG, VAP, PSYS, IBAT, PROCHOT, and ADC features.