SLUSG46 March   2026 BQ25785

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2578X
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi-dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  System Voltage Maximum Regulation (SYS_MAX)
        6. 7.3.26.6  Battery Overvoltage Protection (BATOVP)
        7. 7.3.26.7  Battery Charge Overcurrent Protection (BATCOC)
        8. 7.3.26.8  Battery Discharge Overcurrent Protection (BATDOC)
        9. 7.3.26.9  BATFET Charge Current Clamp Protection Under LDO Regulation Mode
        10. 7.3.26.10 Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 SMBus Interface
        1. 7.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 7.5.1.2 Timing Diagrams
    6. 7.6 BQ25785 Register Map
    7. 7.7 BQ25785 Registers
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Layout Example Reference Top View
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Input Capacitor

The input capacitor has enough ripple current rating to absorb input switching ripple current. The worst-case RMS ripple current is half of the charging current (plus system current if there is any system load) when the duty cycle is 0.5 in buck mode. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and can be estimated by Equation 7:

Equation 7. I C I N = I C H G × D × 1 - D

Low ESR ceramic capacitor, such as X7R or X5R, is preferred for input decoupling capacitor and must be placed in front of RAC current sensing and as close as possible to the power stage half bridge MOSFETs. Capacitance after RAC, before the power stage half bridge, must be limited to 10μF+10nF+1nF as shown in the Figure 8-4 diagram. The voltage rating of the capacitor must be higher than the normal input voltage level. A 35V rating or higher capacitor is preferred for a 28V input voltage. A minimum of 10 pieces of 10µF 0603 size capacitors are suggested for the 28V/140W adapter design. A 50V rating or higher capacitor is preferred for 36V input voltage. A minimum of 10×10μF 0805 capacitors are needed when power reaches 36V/180W. Under different input voltage, the minimum input capacitance requirement is summarized in the following corresponding table. For quasi-dual phase, spread the MLCC capacitors before RAC_A and RAC_B. 1×10nF+1nF 0402 package MLCC capacitors (EMI filter purpose) are recommended to be placed as close as possible to both phase A and phase B half bridge MOSFETs.

Ceramic capacitors show a DC-bias effect. This effect reduces the effective capacitance when a DC-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect can lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's datasheet about the derating performance with a DC-bias voltage applied. Selecting a higher voltage rating or nominal capacitance value can be necessary to get the required capacitance value at the operating point. Tantalum capacitors (POSCAP) can avoid DC-bias effect and temperature variation affect, which is recommended especially for a 28V to 48V higher power application.

Table 8-2 Input Capacitance Requirement for 28V/140W System
28V/140W SYSTEM MINIMUM TYPICAL MAXIMUM
Effective input capacitance

6μF (MLCC) OTG is not needed

8μF (MLCC) OTG is needed

6μF (MLCC) + 15μF (POSCAP) 6μF (MLCC) + 2×33μF (POSCAP)
Practical input capacitors configuration

10×10μF OTG is not needed

(0603 35V MLCC derating to around 6% under 28V bias voltage)

10×10μF (0603 35V MLCC derating to around 6% under 28V bias voltage )

1×15μF (2917 35V POSCAP)

10×10μF (0603 35V MLCC derating to around 6% under 28V bias voltage )

2×33μF (2917 35V POSCAP)
Table 8-3 Input Capacitance Requirement for 36V/180W System
36V/180W SYSTEM MINIMUM TYPICAL MAXIMUM
Effective input capacitance 8μF (MLCC) 8μF (MLCC) + 15μF (POSCAP) 8μF (MLCC) + 2×33μF (POSCAP)
Practical input capacitors configuration

10×10μF (0805 50V MLCC derating to around 8% under 36V bias voltage)

10×10μF (0805 50V MLCC derating to around 8% under 36V bias voltage)

1×15μF (2917 50V POSCAP)

10×10μF (0805 50V MLCC derating to around 8% under 36V bias voltage)

2×33μF (2917 50V POSCAP)