SLUSG46 March 2026 BQ25785
PRODUCTION DATA
Table 7-15 lists the memory-mapped registers for the BQ25785 registers. All register offset addresses not listed in Table 7-15 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 12h | REG0x12_ChargeOption0 | ChargeOption0() | Section 7.7.1 |
| 14h | REG0x14_CHARGE_CURRENT | CHARGE_CURRENT() | Section 7.7.2 |
| 15h | REG0x15_CHARGE_VOLTAGE | CHARGE_VOLTAGE() | Section 7.7.3 |
| 17h | REG0x17_ChargeProfile | ChargeProfile() | Section 7.7.4 |
| 18h | REG0x18_GateDrive | GateDrive() | Section 7.7.5 |
| 19h | REG0x19_ChargeOption5 | ChargeOption5() | Section 7.7.6 |
| 1Ah | REG0x1A_AutoCharge | AutoCharge() | Section 7.7.7 |
| 1Bh | REG0x1B_ChargerStatus0 | ChargerStatus0() | Section 7.7.8 |
| 20h | REG0x20_ChargerStatus1 | ChargerStatus1() | Section 7.7.9 |
| 21h | REG0x21_Prochot_Status_Register | Prochot Status Register | Section 7.7.10 |
| 22h | REG0x22_IIN_DPM | IIN_DPM() | Section 7.7.11 |
| 23h | REG0x23_ADC_VBUS | ADC_VBUS() | Section 7.7.12 |
| 24h | REG0x24_ADC_IBAT | ADC_IBAT() | Section 7.7.13 |
| 25h | REG0x25_ADC_IIN | ADC_IIN() | Section 7.7.14 |
| 26h | REG0x26_ADC_VSYS | ADC_VSYS() | Section 7.7.15 |
| 27h | REG0x27_ADC_VBAT | ADC_VBAT() | Section 7.7.16 |
| 28h | REG0x28_ADC_PSYS | ADC_PSYS() | Section 7.7.17 |
| 29h | REG0x29_ADC_CMPIN_TR | ADC_CMPIN_TR() | Section 7.7.18 |
| 30h | REG0x30_ChargeOption1 | ChargeOption1() | Section 7.7.19 |
| 31h | REG0x31_ChargeOption2 | ChargeOption2() | Section 7.7.20 |
| 32h | REG0x32_ChargeOption3 | ChargeOption3() | Section 7.7.21 |
| 33h | REG0x33_ProchotOption0_Register | ProchotOption0 Register | Section 7.7.22 |
| 34h | REG0x34_ProchotOption1 | ProchotOption1() | Section 7.7.23 |
| 35h | REG0x35_ADCOption | ADCOption() | Section 7.7.24 |
| 36h | REG0x36_ChargeOption4 | ChargeOption4() | Section 7.7.25 |
| 37h | REG0x37_Vmin_Active_Protection | Vmin Active Protection() | Section 7.7.26 |
| 3Bh | REG0x3B_OTG_VOLTAGE | OTG_VOLTAGE() | Section 7.7.27 |
| 3Ch | REG0x3C_OTG_CURRENT | OTG_CURRENT() | Section 7.7.28 |
| 3Dh | REG0x3D_VINDPM | VINDPM() | Section 7.7.29 |
| 3Eh | REG0x3E_VSYS_MIN | VSYS_MIN() | Section 7.7.30 |
| 3Fh | REG0x3F_IIN_HOST | IIN_HOST() | Section 7.7.31 |
| 60h | REG0x60_AUTOTUNE_READ | AUTOTUNE_READ() | Section 7.7.32 |
| 61h | REG0x61_AUTOTUNE_FORCE | AUTOTUNE_FORCE() | Section 7.7.33 |
| 62h | REG0x62_GM_ADJUST_FORCE | GM_ADJUST_FORCE() | Section 7.7.34 |
| FDh | REG0xFD_VIRTUAL_CONTROL | VIRTUAL_CONTROL() | Section 7.7.35 |
| FEh | REG0xFE_Manufacture_ID | Manufacture ID | Section 7.7.36 |
| FFh | REG0xFF_Device_ID | Device ID | Section 7.7.37 |
Complex bit access types are encoded to fit into small table cells. Table 7-16 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
REG0x12_ChargeOption0 is shown in Figure 7-14 and described in Table 7-17.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EN_LWPWR | WDTMR_ADJ | IIN_DPM_AUTO_DISABLE | OTG_ON_CHRGOK | EN_OOA | PWM_FREQ | EN_BATOVP | |
| R/W-1h | R/W-3h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-1h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EN_CMP_LATCH | VSYS_UVP_ENZ | EN_LEARN | IADPT_GAIN | IBAT_GAIN | EN_LDO | EN_IIN_DPM | CHRG_INHIBIT |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-1h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | EN_LWPWR | R/W | 1h | Low Power Mode enable
0b = Disable Low Power Mode. Device in performance mode with battery only. The PROCHOT, IADPT/IBAT/PSYS and comparator follow corresponding register setting, REGN is on with full capacity. 1b = Enable Low Power Mode. Device in low power mode with battery only for lowest quiescent current. The PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. ADC is not available in Low Power Mode. Independent comparator can be enabled by setting EN_LWPWR_CMP to 1b. REGN can be enabled through EN_REGN_LWPWR=1b with 5mA current capability to save quiescent current. |
| 14-13 | WDTMR_ADJ | R/W | 3h | WATCHDOG Timer Adjust Set maximum delay between consecutive EC host write of charge voltage or charge current command. If device does not receive a write on the CHARGE_VOLTAGE() or the CHARGE_CURRENT() within the watchdog time period, the charger is suspended by setting the CHARGE_CURRENT() to 0mA. After expiration, the timer resumes upon the write of CHARGE_CURRENT(), CHARGE_VOLTAGE() ,WDTMR_ADJ or WD_RST=1b. The charger resumes if the values are valid. 00b = Disable 01b = 5 sec 10b = 88 sec 11b = 175 sec |
| 12 | IIN_DPM_AUTO_DISABLE | R/W | 0h | IIN_DPM Auto Disable When CELL_BATPRES pin is LOW, the charger automatically disables the IIN_DPM function by setting EN_IIN_DPM to 0. The host can enable IIN_DPM function later by writing EN_IIN_DPM bit to 1. 0b = Disable 1b = Enable |
| 11 | OTG_ON_CHRGOK | R/W | 0h | Add OTG to CHRG_OK Drive CHRG_OK to HIGH when the device is in OTG mode. 0b = Disable 1b = Enable |
| 10 | EN_OOA | R/W | 1h | Out-of-Audio Enable
0b = No Limit 1b = Set minimum PFM frequency above 20kHz to avoid audio noise |
| 9 | PWM_FREQ | R/W | 1h | Switching Frequency Selection: Recommend 600kHz with 2.2µH, 800kHz with 1.5µH. After charger POR, the MODE pin programming process makes one time change on frequency selection. Note: Frequency is not allowed to change on the fly has to be changed when converter is HIZ. 0b = 800kHz 1b = 600kHz |
| 8 | EN_BATOVP | R/W | 1h | Enable BATOVP protection:
0b = Disable 1b = Enable |
| 7 | EN_CMP_LATCH | R/W | 0h | Enable Latch of Independent Comparator. Comparator output with effective low. If enabled in PROCHOT profile PP_CMP=1b, STAT_COMP bit keep 1b after triggered until read by host and clear. host can clear CMPOUT pin by toggling this EN_CMP_LATCH bit
0b = No Latch 1b = Latch |
| 6 | VSYS_UVP_ENZ | R/W | 0h | To disable system under voltage protection.
0b = Enable 1b = Disable |
| 5 | EN_LEARN | R/W | 0h | LEARN mode function enable:
0b = Disable 1b = Enable |
| 4 | IADPT_GAIN | R/W | 0h | IADPT Amplifier Ratio The ratio of voltage on IADPT and voltage across ACP and ACN. 0b = 20x 1b = 40x |
| 3 | IBAT_GAIN | R/W | 1h | IBAT Amplifier Ratio The ratio of voltage on IBAT and voltage across SRP and SRN 0b = 8x 1b = 64x |
| 2 | EN_LDO | R/W | 1h | LDO Mode Enable When battery voltage is below VSYS_MIN(), the charger is in pre-charge with LDO mode enabled. 0b = Disable LDO mode, BATFET fully ON when charge is enabled and VSYS_MIN() regulation is not effective unless VBAT<5V and system is regulated at 5V. When charge is disabled, BATFET is fully off and system is regulated at VBAT+160mV. 1b = Enable LDO mode, Precharge current is set by the lower setting of CHARGE_CURRENT() and IPRECHG(). The system is regulated by the VSYS_MIN() register. |
| 1 | EN_IIN_DPM | R/W | 1h | IIN_DPM Enable Host writes this bit to enable IIN_DPM regulation loop. When the IIN_DPM is disabled by the charger (refer to IIN_DPM_AUTO_DISABLE), this bit goes LOW. Under OTG mode, this bit is also used to enable/disable IOTG regulation. 0b = Disable 1b = Enable |
| 0 | CHRG_INHIBIT | R/W | 0h | Charge Inhibit When this bit is 0, battery charging starts with valid values in the CHARGE_VOLTAGE() and CHARGE_CURRENT(). 0b = Enable 1b = Inhibit |
REG0x14_CHARGE_CURRENT is shown in Figure 7-15 and described in Table 7-18.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CHARGE_CURRENT | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHARGE_CURRENT | RESERVED | ||||||
| R/W-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R | 0h | Reserved |
| 13-3 | CHARGE_CURRENT | R/W | 0h | Charge current setting with 5mΩ sense resistor (non-zero value lower than 128mA is treated as 128mA): Note when 2mΩ is chosen at RSNS_RSR=1b maximum charge current is clamped at 5DCh (30A with 20mA LSB). Under below scenarios CHARGE_CURRENT is reset to 0A: 1)BATCOC fault. 2)Charge Voltage() is written 0V 3)CELL_BATPRES going low(Battery removal) 4)STAT_AC is not valid(Adapter removal) 5)Watch dog event trigger 6) Autonomous charging get terminated (CHRG_STAT =111b) 7) Safety timer trigger Note: Writing value beyond clamp high/low actually sets register to the clamp high/low value . POR: 0mA (0h) Range: 0mA-16320mA (0h-7F8h) Clamped High Bit Step: 8mA |
| 2-0 | RESERVED | R | 0h | Reserved |
REG0x15_CHARGE_VOLTAGE is shown in Figure 7-16 and described in Table 7-19.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CHARGE_VOLTAGE | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHARGE_VOLTAGE | RESERVED | ||||||
| R/W-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14-2 | CHARGE_VOLTAGE | R/W | 0h | Charge voltage setting Note: Writing non-zero value beyond clamp high/low actually sets register to the clamp high/low value. Writing 0V does not change CHARGE_VOLTAGE() but resets CHARGE_CURRENT() to 0A POR: 0mV (0h) Range: 5000mV-23000mV (4E2h-1676h) Clamped Low Clamped High Bit Step: 4mV Mode: 2s 8400mV POR: 8400mV (834h) Mode: 3s 12600mV POR: 12600mV (C4Eh) Mode: 4s 16800mV POR: 16800mV (1068h) Mode: 5s 21000mV POR: 21000mV (1482h) |
| 1-0 | RESERVED | R | 0h | Reserved |
REG0x17_ChargeProfile is shown in Figure 7-17 and described in Table 7-20.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IPRECHG | |||||||
| R/W-30h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ITERM | |||||||
| R/W-20h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | IPRECHG | R/W | 30h | Maximum precharge current clamp setting with 5mΩ sense resistor(The lower setting of CHARGE_CURRENT() and IPRECHG determine the practical precharge current when VBAT< VSYS_MIN()): Note when 2mΩ sense resistor is chosen RSNS_RSR=1b, then the IPRECHG() upper clamp is 66H to limit BATFET thermal dissipation. Note: Writing value beyond clamp high/low actually sets register to the clamp high/low value . POR: 384mA (30h) Range: 128mA-2016mA (10h-FCh) Clamped Low Clamped High Bit Step: 8mA |
| 7-0 | ITERM | R/W | 20h | Termination current setting with 5mΩ sense resistor: Note: Writing value beyond clamp high/low sets register to the clamp high/low value . POR: 256mA (20h) Range: 128mA-2016mA (10h-FCh) Clamped Low Clamped High Bit Step: 8mA |
REG0x18_GateDrive is shown in Figure 7-18 and described in Table 7-21.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| HIDRV1_STAT | LODRV1_STAT | RESERVED | BATOVP_EXTEND | ||||
| R/W-3h | R/W-3h | R-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HIDRV2_STAT | LODRV2_STAT | VSYS_REG_SLOW | RESERVED | ||||
| R/W-3h | R/W-3h | R/W-0h | R-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | HIDRV1_STAT | R/W | 3h | Suggested HIDRV1_A and HIDRV1_B HS MOSFET gate drive strength adjustment for both turn on and turn off: (Note: Under battery only mode when REGN is on reduce this gate drive strength can help reduce leakage to VBUS, code 000b can totally mitigate the leakage path)
000b = Scale0 (Vgs=4.5V typical Qg range:0-5nC) 001b = Scale1(Vgs=4.5V typical Qg range:5-13nC ) 010b = Scale2 (Vgs=4.5V typical Qg range:13-21nC ) 011b = Scale3(Vgs=4.5V typical Qg range:21-29nC) 100b = Scale4 (Vgs=4.5V typical Qg range:29-37nC) 101b = Scale5(Vgs=4.5V typical Qg range:37-45nC) 110b = Scale6 (Vgs=4.5V typical Qg range:45-53nC) 111b = Scale7(Vgs=4.5V typical Qg range: >53nC) |
| 12-10 | LODRV1_STAT | R/W | 3h | Suggested LODRV1_A and LODRV1_B LS MOSFET gate drive strength adjustment for both turn on and turn off:
000b = Scale0 (Vgs=4.5V typical Qg range:0-5nC) 001b = Scale1(Vgs=4.5V typical Qg range:5-13nC ) 010b = Scale2 (Vgs=4.5V typical Qg range:13-21nC ) 011b = Scale3(Vgs=4.5V typical Qg range:21-29nC) 100b = Scale4 (Vgs=4.5V typical Qg range:29-37nC) 101b = Scale5(Vgs=4.5V typical Qg range:37-45nC) 110b = Scale6 (Vgs=4.5V typical Qg range:45-53nC) 111b = Scale7(Vgs=4.5V typical Qg range: >53nC) |
| 9 | RESERVED | R | 0h | Reserved |
| 8 | BATOVP_EXTEND | R/W | 0h | Enable BATOVP for both charge enable and disable scenarios including AC+battery and battery only. 0b: BATOVP is only active when charge is enabled(BATFET is turned on) when EN_BATOVP=1b 1b: BATOVP is active as long as EN_BATOVP=1b, no matter charge is enabled or not(BATFET is on or off) 0b = Disable 1b = Enable |
| 7-5 | HIDRV2_STAT | R/W | 3h | Suggested HIDRV2 HS MOSFET gate drive strength adjustment for both turn on and turn off: (Note: Under battery only mode when REGN is on reduce this gate drive strength can help reduce leakage to VBUS, code 000b can totally mitigate the leakage path)
000b = Scale0 (Vgs=4.5V typical Qg range:0-5nC) 001b = Scale1(Vgs=4.5V typical Qg range:5-13nC ) 010b = Scale2 (Vgs=4.5V typical Qg range:13-21nC ) 011b = Scale3(Vgs=4.5V typical Qg range:21-29nC) 100b = Scale4 (Vgs=4.5V typical Qg range:29-37nC) 101b = Scale5(Vgs=4.5V typical Qg range:37-45nC) 110b = Scale6 (Vgs=4.5V typical Qg range:45-53nC) 111b = Scale7(Vgs=4.5V typical Qg range: >53nC) |
| 4-2 | LODRV2_STAT | R/W | 3h | Suggested LODRV2 LS MOSFET gate drive strength adjustment for both turn on and turn off:
000b = Scale0 (Vgs=4.5V typical Qg range:0-5nC) 001b = Scale1(Vgs=4.5V typical Qg range:5-13nC ) 010b = Scale2 (Vgs=4.5V typical Qg range:13-21nC ) 011b = Scale3(Vgs=4.5V typical Qg range:21-29nC) 100b = Scale4 (Vgs=4.5V typical Qg range:29-37nC) 101b = Scale5(Vgs=4.5V typical Qg range:37-45nC) 110b = Scale6 (Vgs=4.5V typical Qg range:45-53nC) 111b = Scale7(Vgs=4.5V typical Qg range: >53nC) |
| 1 | VSYS_REG_SLOW | R/W | 0h | System regulation loop bandwidth slow down to reduce input current overshoot during load transient:
0b = Disable 1b = Enable |
| 0 | RESERVED | R | 0h | Reserved |
REG0x19_ChargeOption5 is shown in Figure 7-19 and described in Table 7-22.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PTM_EXIT_LIGHT_LOAD | WD_RST | CMPIN_TR_SELECT | REGN_EXT | EN_REGN_LWPWR | BATCOC_CONFIG | RESERVED | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-3h | R-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SINGLE_DUAL_TRANS_TH | FORCE_SINGLE | PH_ADD_DEG | PH_DROP_DEG | ||||
| R/W-4h | R/W-0h | R/W-1h | R/W-1h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | PTM_EXIT_LIGHT_LOAD | R/W | 0h | Enable PTM auto exit under light load:
0b = Disable 1b = Enable |
| 14 | WD_RST | R/W | 0h | Reset watch dog timer control:
0b = Normal 1b = Reset(bit goes back to 0 after timer reset) |
| 13 | CMPIN_TR_SELECT | R/W | 0h | CPMIN_TS pin function selection:
0b = CPMIN function 1b = TREG function |
| 12 | REGN_EXT | R/W | 0h | Enable external 5V overdrive for REGN:
0b = Disabled external 5V over drive 1b = Enable external 5V over drive |
| 11 | EN_REGN_LWPWR | R/W | 0h | Enable REGN with scale down current 5mA capability under battery only and low power mode:
0b = Disabled REGN under battery only low power mode 1b = Enable REGN under battery only low power mode |
| 10-9 | BATCOC_CONFIG | R/W | 3h | Disable BATCOC and configure BATCOC thresholds across SRP-SRN:
00b = Disable 01b = 50mV 10b = 75mV 11b = 100mV |
| 8 | RESERVED | R | 0h | Reserved |
| 7-5 | SINGLE_DUAL_TRANS_TH | R/W | 4h | Buck mode single to dual phase transition threshold adjustment based on output load current: (When Quasi dual phase is chosen at MODE pin programming) Note from dual phase to single phase transition the load current threshold is 1A lower than this configuration as hysteresis.
000b = Force Dual Phase Operation 001b = 3A 010b = 4A 011b = 5A 100b = 6A 101b = 7A 110b = 8A 111b = 9A |
| 4 | FORCE_SINGLE | R/W | 0h | Force single phase operation under buck mode when quasi dual phase is chosen through MODE pin programming:
0b = Automatically transit to dual phase based on SINGLE_DUAL_TRANS_TH threshold option 1b = Force Single Phase under buck mode |
| 3-2 | PH_ADD_DEG | R/W | 1h | Adjust single phase to dual phase( phase adding transition) deglitch time:
00b = 0.727µs(Min)/1.7µs(Typ)/2.67µs(Max) 01b = 2.91µs(Min)/5.5µs(Typ)/8µs(Max) 10b = 11.6µs(Min)/20µs(Typ)/29.3µs(Max) 11b = 46.6µs(Min)/86µs(Typ)/115µs(Max) |
| 1-0 | PH_DROP_DEG | R/W | 1h | Adjust dual phase to single phase( phase dropping transition) deglitch time:
00b = 70µs(Min)/93µs(Typ)/115µs(Max) 01b = 1.12ms(Min)/1.5ms(Typ)/1.82ms(Max) 10b = 8.94ms(Min)/11ms(Typ)/1.46ms(Max) 11b = 71.5ms(Min)/94ms(Typ)/117ms(Max) |
REG0x1A_AutoCharge is shown in Figure 7-20 and described in Table 7-23.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EN_AUTO_CHG | CHRG_OK_INT | VRECHG | CHG_TMR | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-1h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EN_TMR2X | EN_CHG_TMR | EN_TREG | PP_THERMAL | STAT_THERMAL | THERMAL_DEG | ACOV_ADJ | |
| R/W-1h | R/W-1h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-2h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | EN_AUTO_CHG | R/W | 0h | Automatic charge control (recharge and terminate battery charging automatically):
0b = Disable 1b = Enable |
| 14 | CHRG_OK_INT | R/W | 0h | Enable CHRG_OK pin for interrupt function:
0b = Disable(CHRG_OK pin is not pulled low when CHRG_STAT bits changes) 1b = Enable(CHRG_OK pin is pulled low for minimum 256us when CHRG_STAT bits changes) |
| 13-10 | VRECHG | R/W | 0h | Battery automatic recharge threshold below CHARGE_VOLTAGE():
POR: 50mV (0h) Range: 50mV-800mV (0h-Fh) Bit Step: 50mV Offset: 50mV Mode: 2s 200mV POR: 200mV (3h) Mode: 3s 300mV POR: 300mV (5h) Mode: 4s 400mV POR: 400mV (7h) Mode: 5s 500mV POR: 500mV (9h) |
| 9-8 | CHG_TMR | R/W | 1h | Automatic Charge Safety Timer control:
00b = 5hr 01b = 8hr 10b = 12hr 11b = 24hr |
| 7 | EN_TMR2X | R/W | 1h | Charge Safety Timer speed control: (Note changing the state of EN_TMR2X only impacts the rate at which the counter is counting and has no effect on any existing accumulated count)
0b = Timer always counts normally 1b = Timer slowed by 2x during VINDPM/IINDPM/TREG regulation |
| 6 | EN_CHG_TMR | R/W | 1h | Enable charge safety timer:
0b = Disable 1b = Enable |
| 5 | EN_TREG | R/W | 0h | Enable temperature regulation function and pull down CMPOUT pin to GND if CMPIN_TR_SELECT=1b. If CMPIN_TR_SELECT=0b, then EN_TREG is not effective.
0b = Disable temperature regulation function 1b = Enable temperature regulation function |
| 4 | PP_THERMAL | R/W | 0h | Enable temperature regulation(TREG) for PROCHOT profile.
0b = Disable 1b = Enable |
| 3 | STAT_THERMAL | R | 0h | PROCHOT profile status bit for TREG thermal overheat (CMPIN_TR< 1.1V). The status is latched until a read from host.
0b = Not Triggered 1b = Triggered |
| 2 | THERMAL_DEG | R/W | 0h | Adjust TREG thermal deglitch time to trigger prochot profile pull down pulse.
0b = 0.76sec(min)/0.965sec(Typ.)/1.17sec(max) 1b = 95.3ms(min)/121ms(Typ.)/146ms(max) |
| 1-0 | ACOV_ADJ | R/W | 2h | ACOV protection threshold adjustment:
00b = reserved 01b = 27V(20V SPR ) 10b = 33V(28V EPR ) 11b = 41V(36V EPR) |
REG0x1B_ChargerStatus0 is shown in Figure 7-21 and described in Table 7-24.
Return to the Summary Table.
ChargeStatus0()
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHRG_STAT | CHG_TMR_STAT | TREG_STAT | MODE_STAT | ||||
| R-0h | R-0h | R-0h | R-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FAULT_BATOVP | RESERVED | FAULT_OCP | RESERVED | FAULT_REGN | RESERVED | ||
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | CHRG_STAT | R | 0h | Charge Cycle Status
000b = Not Charging 001b = Trickle Charge (VBAT<VBAT_SHORT) 010b = Pre-Charge (VBAT<VSYS_MIN) 011b = Fast Charge(CC mode) 100b = Fast Charge(CV mode) 101b = Reserve1 110b = Reserve2 111b = Charge Termination Done |
| 12 | CHG_TMR_STAT | R | 0h | Charge safety timer status
0b = Normal 1b = Charge safety timer expired |
| 11 | TREG_STAT | R | 0h | Temperature regulation status
0b = Not in temperature regulation(TREG) 1b = In temperature regulation(TREG) |
| 10-8 | MODE_STAT | R | 0h | MODE pin program status
000b = Quasi Dual Phase/Normal Compensation/Fsw-600kHz 001b = Quasi Dual Phase/Normal Compensation/Fsw-800kHz 010b = Quasi Dual Phase/Slow Compensation/Fsw-600kHz 011b = Quasi Dual Phase/Slow Compensation/Fsw-800kHz 100b = NA/Normal Compensation/Fsw-600kHz 101b = NA/Normal Compensation/Fsw-800kHz 110b = NA/Slow Compensation/Fsw-600kHz 111b = NA/Slow Compensation/Fsw-800kHz |
| 7 | FAULT_BATOVP | R | 0h | The status are latched until a read from host, , if the fault still exist during host read this bit is kept at 1b. However after host read fault status one time, this bit is automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed.
0b = No Fault 1b = Fault |
| 6 | RESERVED | R | 0h | Reserved |
| 5 | FAULT_OCP | R | 0h | The status are latched until a read from host, if the fault still exist during host read this bit is kept at 1b. However after host read fault status one time, this bit is automatically reset when the original fault is cleared.
0b = No Fault 1b = Fault |
| 4 | RESERVED | R | 0h | Reserved |
| 3 | FAULT_REGN | R | 0h | The status are latched until a read from host, , if the fault still exist during host read this bit is kept at 1b. However after host read fault status one time, this bit is automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed.
0b = No Fault 1b = Fault |
| 2-0 | RESERVED | R | 0h | Reserved |
REG0x20_ChargerStatus1 is shown in Figure 7-22 and described in Table 7-25.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| STAT_AC | ICO_DONE | IN_VAP | IN_VINDPM | IN_IIN_DPM | FAULT_SC_VBUSACP | FAULT_BATCOC | IN_OTG |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FAULT_ACOV | FAULT_BATDOC | FAULT_ACOC | FAULT_SYSOVP | FAULT_VSYS_UVP | FAULT_FRC_CONV_OFF | FAULT_OTG_OVP | FAULT_OTG_UVP |
| R-0h | R-0h | R-0h | R/W-0h | R/W-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | STAT_AC | R | 0h | Input source status, STAT_AC is active as long as valid VBUS source exist
0b = Not Present 1b = Present |
| 14 | ICO_DONE | R | 0h | After the ICO routine is successfully executed, the bit goes 1.
0b = Not Complete 1b = Complete |
| 13 | IN_VAP | R | 0h | Digital status bit indicates VAP has been enabled(1) or disabled(0). The enable of VAP mode only follows the host command, which is not blocked by any status of /PROCHOT. The exit of VAP mode also follows the host command, except that any faults exits VAP mode automatically. STAT_EXIT_VAP becomes 1 which pulls low /PROCHOT until host clear. The host can enable VAP by setting EN_OTG pin high and OTG_VAP_MODE=0b, disable VAP by setting either EN_OTG pin low or OTG_VAP_MOD=1b. When IN_VAP bit goes 0->1, charger disables VinDPM, IIN_DPM, ILIM pin, disable PP_ACOK if it is enabled, enable PP_VSYS if it is disabled. When IN_VAP bit goes 1->0, charger enables VinDPM, IIN_DPM, ILIM pin 0b = Not Operated 1b = Operated |
| 12 | IN_VINDPM | R | 0h | VINDPM/ VOTG Status
0b = Charger is not in VINDPM during forward mode, or voltage regulation during OTG mode 1b = Charger is in VINDPM during forward mode, or voltage regulation during OTG mode |
| 11 | IN_IIN_DPM | R | 0h | IIN_DPM / IOTG Status
0b = Not In IIN_DPM 1b = In IIN_DPM |
| 10 | FAULT_SC_VBUSACP | R | 0h | The faults are latched until a read from host, if the fault still exist during host read this bit is kept at 1b. However after host read fault status one time, this bit is automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed.
0b = No Fault 1b = Fault |
| 9 | FAULT_BATCOC | R | 0h | The faults are latched until a read from host after 1 second after triggering. To recover charge, EC also need to re-write non zero value into CHARGE_CURRENT() register.
0b = No Fault 1b = Fault |
| 8 | IN_OTG | R | 0h | OTG
0b = Not In OTG 1b = In OTG |
| 7 | FAULT_ACOV | R | 0h | The faults are latched until a read from host, if the fault still exist during host read this bit is kept at 1b. However after host read fault status one time, this bit is automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed.
0b = No Fault 1b = Fault |
| 6 | FAULT_BATDOC | R | 0h | The faults are latched until a read from host, if the fault still exist during host read this bit is kept at 1b. However after host read fault status one time, this bit is automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed.
0b = No Fault 1b = Fault |
| 5 | FAULT_ACOC | R | 0h | The faults are latched until a read from host, if the fault still exist during host read this bit is kept at 1b. However after host read fault status one time, this bit is automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed.
0b = No Fault 1b = Fault |
| 4 | FAULT_SYSOVP | R/W | 0h | SYSOVP fault status and Clear When the SYSOVP occurs, this bit is set HIGH. As long as this bit is high, the converter is disabled. After the SYSOVP is removed, the user must write a 0 to this bit or unplug the adapter to clear the SYSOVP condition to enable the converter again. 0b = No Fault 1b = Fault |
| 3 | FAULT_VSYS_UVP | R/W | 0h | VSYS_UVP fault status is latched until a clear from host by writing this bit to 0. As long as this bit is high, the converter is disabled. After the VSYS_UVP is removed, the user must write a 0 to this bit or unplug the adapter to clear the VSYS_UVP condition to enable the converter again. 0b = No Fault 1b = Fault |
| 2 | FAULT_FRC_CONV_OFF | R | 0h | Force converter off when independent comparator is triggered low effective. The faults are latched until a read from host, if the fault still exist during host read this bit is kept at 1b. However after host read fault status one time, this bit is automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed.
0b = No Fault 1b = Fault |
| 1 | FAULT_OTG_OVP | R | 0h | The faults are latched until a read from host, if the fault still exist during host read this bit is kept at 1b. However after host read fault status one time, this bit is automatically reset when the original fault is cleared. In this way hos
0b = No Fault 1b = Fault |
| 0 | FAULT_OTG_UVP | R | 0h | The faults are latched until a read from host, if the fault still exist during host read this bit is kept at 1b. However after host read fault status one time, this bit is automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed.
0b = No Fault 1b = Fault |
REG0x21_Prochot_Status_Register is shown in Figure 7-23 and described in Table 7-26.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EN_PROCHOT_EXT | PROCHOT_WIDTH | PROCHOT_CLEAR | TSHUT | STAT_VAP_FAIL | STAT_EXIT_VAP | |
| R-0h | R/W-0h | R/W-3h | R/W-1h | R-0h | R/W-0h | R/W-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STAT_VINDPM | STAT_COMP | STAT_ICRIT | STAT_INOM | STAT_IDCHG1 | STAT_VSYS | STAT_BATTERY_REMOVAL | STAT_ADAPTER_REMOVAL |
| R/W-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14 | EN_PROCHOT_EXT | R/W | 0h | PROCHOT Pulse Extension Enable. When pulse extension is enabled, keep the PROCHOT pin voltage LOW until host writes PROCHOT_CLEAR= 0b.
0b = Disable 1b = Enable |
| 13-12 | PROCHOT_WIDTH | R/W | 3h | PROCHOT Pulse Width when EN_PROCHOT_EXT = 0b 00b = 83ms(min)/100ms(Typ.)/117ms(max) 01b = 42ms(min)/50ms(Typ.)/58ms(max) 10b = 5ms(min)/6.15ms(Typ.)/7.3ms(max) 11b = 10ms(min)/12.5ms(Typ.)/15ms(max) |
| 11 | PROCHOT_CLEAR | R/W | 1h | PROCHOT Pulse Clear. Clear PROCHOT pulse when EN_PROCHOT_EXT=0b. 0b = Clear PROCHOT pulse and drive /PROCHOT pin HIGH 1b = Idle |
| 10 | TSHUT | R | 0h | TSHUT trigger
0b = Not Triggered 1b = Triggered |
| 9 | STAT_VAP_FAIL | R/W | 0h | This status bit reports a failure to load VBUS 7 consecutive times in VAP mode, which indicates the battery voltage is not always high enough to enter VAP mode, or the VAP loading current settings are too high.
0b = Not is VAP failure 1b = In VAP failure, the charger exits VAP mode, and latches off until the host writes this bit to 0. |
| 8 | STAT_EXIT_VAP | R/W | 0h | Host can exit VAP by setting this bit to 0, or there is a fault.
0b = PROCHOT_EXIT_VAP is not active 1b = PROCHOT_EXIT_VAP is active, PROCHOT pin is low until host writes this status bit to 0 |
| 7 | STAT_VINDPM | R/W | 0h | PROCHOT Profile VINDPM status bit, once triggered 1b, PROCHOT pin is low until host writes this status bit to 0b when PP_VINDPM = 1b.
0b = Not Triggered 1b = Triggered |
| 6 | STAT_COMP | R | 0h | The status is latched until a read from host.
0b = Not Triggered 1b = Triggered |
| 5 | STAT_ICRIT | R | 0h | The status is latched until a read from host.
0b = Not Triggered 1b = Triggered |
| 4 | STAT_INOM | R | 0h | The status is latched until a read from host.
0b = Not Triggered 1b = Triggered |
| 3 | STAT_IDCHG1 | R | 0h | The status is latched until a read from host.
0b = Not Triggered 1b = Triggered |
| 2 | STAT_VSYS | R | 0h | The status is latched until a read from host.
0b = Not Triggered 1b = Triggered |
| 1 | STAT_BATTERY_REMOVAL | R | 0h | The status is latched until a read from host.
0b = Not Triggered 1b = Triggered |
| 0 | STAT_ADAPTER_REMOVAL | R | 0h | The status is latched until a read from host.
0b = Not Triggered 1b = Triggered |
REG0x22_IIN_DPM is shown in Figure 7-24 and described in Table 7-27.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | IIN_DPM | ||||||
| R-0h | R-C8h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IIN_DPM | RESERVED | ||||||
| R-C8h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10-2 | IIN_DPM | R | C8h | Input current setting with 10mΩ sense resistor:
POR: 5000mA (C8h) Range: 400mA-8200mA (10h-148h) Clamped Low Clamped High Bit Step: 25mA |
| 1-0 | RESERVED | R | 0h | Reserved |
REG0x23_ADC_VBUS is shown in Figure 7-25 and described in Table 7-28.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADC_VBUS | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADC_VBUS | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | ADC_VBUS | R | 0h | VBUS ADC reading: (Note: When VBUS plugged in before converter starts up , VBUS ADC channel executes one time to read the no-load VBUS voltage and save the value into ADC_VBUS()) POR: 0mV (0h) Format: 2s Complement Range: 0mV-65534mV (0h-7FFFh) Clamped Low Bit Step: 2mV |
REG0x24_ADC_IBAT is shown in Figure 7-26 and described in Table 7-29.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADC_IBAT | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADC_IBAT | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | ADC_IBAT | R | 0h | IBAT ADC reading with 5mΩ sense resistor: Note the charger only measures discharging current (negative voltage) under battery only or OTG modes, and only measure charging current(positive voltage) when valid adapter is plugged in
POR: 0mA (0h) Format: 2s Complement Range: -32768mA-32767mA (8000h-7FFFh) Bit Step: 1mA |
REG0x25_ADC_IIN is shown in Figure 7-27 and described in Table 7-30.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADC_IIN | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADC_IIN | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | ADC_IIN | R | 0h | IIN ADC reading with 10mΩ sense resistor: current flowing from the adapter to the converter (like in forward mode) is represented as positive and current flowing to the adapter (like in OTG mode) is negative.
POR: 0mA(0h) Format: 2s Complement Range: -16384mA - 16383.5mA (8000h-7FFFh) Bit Step: 0.5mA |
REG0x26_ADC_VSYS is shown in Figure 7-28 and described in Table 7-31.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADC_VSYS | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADC_VSYS | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | ADC_VSYS | R | 0h | VSYS ADC reading:
POR: 0mV (0h) Format: 2s Complement Range: 0mV-65534mV (0h-7FFFh) Clamped Low Bit Step: 2mV |
REG0x27_ADC_VBAT is shown in Figure 7-29 and described in Table 7-32.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADC_VBAT | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADC_VBAT | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | ADC_VBAT | R | 0h | VBAT ADC reading:
POR: 0mV (0h) Format: 2s Complement Range: 0mV-32767mV (0h-7FFFh) Clamped Low Bit Step: 1mV |
REG0x28_ADC_PSYS is shown in Figure 7-30 and described in Table 7-33.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADC_PSYS | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADC_PSYS | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | ADC_PSYS | R | 0h | System Power PSYS ADC reading:
POR: 0mV (0h) Range: 0mV-8191mV (0h-1FFFh) Clamped High Bit Step: 1mV |
REG0x29_ADC_CMPIN_TR is shown in Figure 7-31 and described in Table 7-34.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADC_CMPIN_TR | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADC_CMPIN_TR | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | ADC_CMPIN_TR | R | 0h | CMPIN_TR pin voltage ADC reading:
POR: 0mV (0h) Range: 0mV-8191mV (0h-1FFFh) Clamped High Bit Step: 1mV |
REG0x30_ChargeOption1 is shown in Figure 7-32 and described in Table 7-35.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EN_IBAT | EN_LWPWR_CMP | PSYS_CONFIG | RSNS_RAC | RSNS_RSR | PSYS_RATIO | EN_OTG_BIG_CAP | |
| R/W-0h | R/W-0h | R/W-3h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SYSOVP_MAX | CMP_POL | CMP_DEG | FRC_CONV_OFF | EN_PTM | EN_SHIP_DCHG | EN_SC_VBUSACP | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | EN_IBAT | R/W | 0h | IBAT Enable Enable the IBAT output buffer. In low power mode (EN_LWPWR=1b), IBAT buffer is always disabled regardless of this bit value. 0b = Disable 1b = Enable |
| 14 | EN_LWPWR_CMP | R/W | 0h | Independent Comparator Enable Enable independent comparator under battery only low power mode(EN_LWPWR=1b) 0b = Disable 1b = Enable |
| 13-12 | PSYS_CONFIG | R/W | 3h | PSYS Enable and Definition Register Enable PSYS sensing circuit and output buffer (whole PSYS circuit). In low power mode (EN_LWPWR=1b), PSYS sensing and buffer are always disabled regardless of this bit value. 00b = PBUS+PBAT 01b = PBUS 10b = RESERVED 11b = OFF |
| 11 | RSNS_RAC | R/W | 0h | Input sense resistor RAC.Not recommend change this value during IINDPM/IOTG regulation: Under adapter plugged in: make changes right after converter starts up with light loading and before charge is enabled. With battery only : make changes before EN_OTG pin is pulled up. 0b = 10mW 1b = 5mW |
| 10 | RSNS_RSR | R/W | 0h | Charge sense resistor RSR. Not recommend change this value during ICHG/IPRECHG/BATFET_CLAMP1/BATFET_CLAMP2/BAT_SHORT regulation: Under adapter plugged in: make changes right after converter starts up with light loading and before charge is enabled. With battery only : make changes before EN_OTG pin is pulled up. 0b = 5mW 1b = 2mW |
| 9 | PSYS_RATIO | R/W | 1h | PSYS Gain Ratio of PSYS output current vs total input and battery power. 0b = 0p25uAperW 1b = 1p00uAperW |
| 8 | EN_OTG_BIG_CAP | R/W | 0h | Enable OTG compensation for VBUS effective capacitance larger than 60mF 0b = Disable OTG large VBUS capacitance compensation(Recommended for VBUS effective capacitance smaller than 60mF effective capacitance) 1b = Enable OTG large VBUS capacitance compensation(Recommended for VBUS effective capacitance larger than 60mF effective capacitance) |
| 7 | SYSOVP_MAX | R/W | 0h | Force SYSOVP protection threshold to 27V neglecting CELL_BATPRES pin configuration
0b = Disable 1b = Enable |
| 6 | CMP_POL | R/W | 0h | Independent Comparator output Polarity
0b = When CMPIN_TR is above internal threshold, CMPOUT is LOW (internal hysteresis) 1b = When CMPIN_TR is below internal threshold, CMPOUT is LOW (external hysteresis) |
| 5-4 | CMP_DEG | R/W | 0h | Independent comparator deglitch time, only applied to the falling edge of CMPOUT (HIGH to LOW). 00b = 1us(Not in battery only low power mode)/ 40us(Battery only low power mode) 01b = 2.05ms to 2.73ms 10b = 20.85ms to 27.31ms 11b = 5.34s to 6.99s |
| 3 | FRC_CONV_OFF | R/W | 0h | Force Power Path Off During forward mode with AC plugged in or battery only performance mode, when independent comparator triggers, charger turns off Q1 and Q4 (same as disable converter) so that the system is disconnected from the input source. At the same time, CHRG_OK signal goes to LOW to notify the system. Both FRC_CONV_OFF and CMP_EN are 1b to enable this feature. No need for EN_LWPWR, EN_LWPWR_CMP to be high which are employed under battery only low power mode. 0b = Disable 1b = Enable |
| 2 | EN_PTM | R/W | 0h | PTM enable register is set to 0 by default
0b = Disable 1b = Enable |
| 1 | EN_SHIP_DCHG | R/W | 0h | Discharge SRN for Shipping Mode Used to discharge SRN pin capacitor voltage which is necessary for battery gauge device shipping mode. When this bit is 1, discharge SRN pin down in 340ms with around 20mA current flowing through VSYS pin. When 340ms is over, this bit is reset to 0 automatically. If this bit is written to 0b by host before 340ms expires, VSYS pin stop discharging immediately. After SRN is discharged to 0V the discharge current shuts off automatically to get rid of any negative voltage on SRN pin. Note if after 340ms SRN voltage is still not low enough for battery gauge device entering ship mode, the host can need to write this bit to 1b again to start a new 340ms discharge cycle. 0b = Disable 1b = Enable |
| 0 | EN_SC_VBUSACP | R/W | 1h | SC_VBUSACP protection enable register bit
0b = Disable 1b = Enable |
REG0x31_ChargeOption2 is shown in Figure 7-33 and described in Table 7-36.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PKPWR_TOVLD_DEG | EN_PKPWR_IIN_DPM | EN_PKPWR_VSYS | STAT_PKPWR_OVLD | STAT_PKPWR_RELAX | PKPWR_TMAX | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EN_EXTILIM | EN_ICHG_IDCHG | OCP_SW2_HIGH_RANGE | OCP_SW1X_HIGH_RANGE | EN_ACOC | ACOC_VTH | EN_BATDOC | BATDOC_VTH |
| R/W-1h | R/W-0h | R/W-1h | R/W-1h | R/W-0h | R/W-1h | R/W-1h | R/W-1h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | PKPWR_TOVLD_DEG | R/W | 0h | Input Overload time in Peak Power Mode
00b = 1ms 01b = 2ms 10b = 5ms 11b = 10ms |
| 13 | EN_PKPWR_IIN_DPM | R/W | 0h | Enable Peak Power Mode triggered by input current overshoot. If EN_PKPWR_IIN_DPM and EN_PKPWR_VSYS are 0b, peak power mode is disabled. Upon adapter removal, this bits is reset to 0b.
0b = Disable 1b = Enable |
| 12 | EN_PKPWR_VSYS | R/W | 0h | Enable Peak Power Mode triggered by system voltage under-shoot. If EN_PKPWR_IIN_DPM and EN_PKPWR_VSYS are 0b, peak power mode is disabled. Upon adapter removal, this bits is reset to 0b.
0b = Disable 1b = Enable |
| 11 | STAT_PKPWR_OVLD | R/W | 0h | Indicator that the device is in overloading cycle. Write 0 to get out of overloading cycle. 0b = Not In Peak 1b = In Peak |
| 10 | STAT_PKPWR_RELAX | R/W | 0h | Indicator that the device is in relaxation cycle. Write 0 to get out of relaxation cycle.
0b = Not In Relaxation 1b = In Relaxation |
| 9-8 | PKPWR_TMAX | R/W | 0h | Peak power mode overload and relax cycle time.
00b = 20ms 01b = 40ms 10b = 80ms 11b = 1s |
| 7 | EN_EXTILIM | R/W | 1h | Enable ILIM_HIZ pin to set input current limit
0b = Disable(Input current limit is set by IIN_HOST()) 1b = Enable(Input current limit is set by the lower value of ILIM_HIZ pin and IIN_HOST()) |
| 6 | EN_ICHG_IDCHG | R/W | 0h | IBAT pin monitor selection for discharge current and charge current
0b = IBAT pin as Discharge Current 1b = IBAT pin as Charge Current |
| 5 | OCP_SW2_HIGH_RANGE | R/W | 1h | Over current protection threshold by sensing Q4 Vds. When this fault is continuously triggered 1 switching cycle, converter is latched off. To re-enable converter, need to toggle EN_HIZ bit from 0 to 1 and back to 0.
0b = 150mV 1b = 260mV |
| 4 | OCP_SW1X_HIGH_RANGE | R/W | 1h | Over current protection threshold by sensing RAC resistor across voltage, When this fault is continuously triggered 1 switching cycle, converter is latched off. To re-enable converter, need to toggle EN_HIZ bit from 0 to 1 and back to 0.
0b = 300mV (150mV under VSYS_UVP) for Q1_A and Q1_B 1b = 450mV (300mV under VSYS_UVP) for Q1_A and Q1_B |
| 3 | EN_ACOC | R/W | 0h | ACOC Enable Input overcurrent (ACOC) protection by sensing the voltage across ACP_A and ACN_A plus ACP_B and ACN_B. Upon ACOC (after 250µs blank-out time), converter is disabled. 0b = Disable 1b = Enable |
| 2 | ACOC_VTH | R/W | 1h | ACOC Limit Set ACOC threshold as percentage of ILIM2_VTH with current sensed from RAC. 0b = 1.33 1b = 2 |
| 1 | EN_BATDOC | R/W | 1h | BATDOC Enable Battery discharge overcurrent (BATDOC) protection by sensing the voltage across SRN and SRP. Upon BATDOC, converter is disabled. 0b = Disable 1b = Enable |
| 0 | BATDOC_VTH | R/W | 1h | Set battery discharge overcurrent threshold as percentage of PROCHOT battery discharge current limit. 0b = 2 1b = 3 |
REG0x32_ChargeOption3 is shown in Figure 7-34 and described in Table 7-37.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EN_HIZ | REG_RESET | DETECT_VINDPM | EN_OTG | EN_ICO_MODE | EN_PORT_CTRL | EN_VSYS_MIN_SOFT_SR | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BATFET_ENZ | VSYSMAX_CLAMP_EN | OTG_VAP_MODE | IL_AVG | CMP_EN | BATFETOFF_HIZ | PSYS_OTG_IDCHG | |
| R/W-0h | R/W-1h | R/W-1h | R/W-2h | R/W-1h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | EN_HIZ | R/W | 0h | Device Hi-Z Mode Enable When the charger is in Hi-Z mode, the device draws minimal quiescent current. With VBUS above UVLO. REGN LDO stays on, and system powers from battery. 0b = Disable 1b = Enable |
| 14 | REG_RESET | R/W | 0h | Reset Registers All the R/W and R registers go back to the default setting except: CHRG_STAT, MODE_STAT, HIDRV1_STAT, LODRV1_STAT, HIDRV2_STAT, LODRV2_STAT, PWM_FREQ 0b = Idle 1b = Reset |
| 13 | DETECT_VINDPM | R/W | 0h | Set VINDPM threshold based on VBUS measurement result minus 1.28V, Converter is disabled to measure VBUS. After VBUS measurement is done, VINDPM() is written with value VBUS-1.28V. Then this bit goes back to 0 and converter starts.
0b = Idle 1b = Measure VIN, write VIN-1.28V to VINDPM |
| 12 | EN_OTG | R/W | 0h | OTG Mode Enable Enable device in OTG mode when EN_OTG pin is HIGH. 0b = Disable 1b = Enable |
| 11 | EN_ICO_MODE | R/W | 0h | Enable ICO Algorithm
0b = Disable 1b = Enable |
| 10 | EN_PORT_CTRL | R/W | 1h | Enable BATFET control for dual port application:
0b = Disable BATFET control by HIZ BATDRV pin 1b = Enable BATFET control by active BATDRV pin |
| 9-8 | EN_VSYS_MIN_SOFT_SR | R/W | 1h | VSYS_MIN soft slew rate control for VSYS_MIN step up transition. Note for step down doesn't need the soft transition.
00b = Disable 01b = 6.25mV/us 10b = 3.125mV/us 11b = 1.5625mV/us |
| 7 | BATFET_ENZ | R/W | 0h | Turn off BATFET under battery only low power mode. When not in low power mode like OTG or with AC plugged in, the bit configuration is neglected and not effective.
0b = Not force turn off BATFET 1b = Force turn off BATFET |
| 6 | VSYSMAX_CLAMP_EN | R/W | 1h | Clamp VSYSMAX regulation target to avoid VSYS rise up together with VBAT when no battery is plugged in. 0b = Disable 1b = Enable |
| 5 | OTG_VAP_MODE | R/W | 1h | The selection of the external EN_OTG pin control.
0b = VAP Mode 1b = OTG Mode |
| 4-3 | IL_AVG | R/W | 2h | 4 levels inductor average current clamp.
00b = 10A 01b = 18A 10b = 24A 11b = Disable(internal 30A limit) |
| 2 | CMP_EN | R/W | 1h | Enable Independent Comparator with effective low.
0b = Disable 1b = Enable |
| 1 | BATFETOFF_HIZ | R/W | 0h | Turn off BATFET during HIZ mode.
0b = On 1b = Off |
| 0 | PSYS_OTG_IDCHG | R/W | 0h | PSYS definition during OTG mode.
0b = PSYS as battery discharge power minus OTG output power 1b = PSYS as battery discharge power only |
REG0x33_ProchotOption0_Register is shown in Figure 7-35 and described in Table 7-38.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ILIM2_VTH | ICRIT_DEG | PROCHOT_VINDPM_80_90 | |||||
| R/W-9h | R/W-1h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VSYS_TH1 | INOM_DEG | LOWER_PROCHOT_VINDPM | |||||
| R/W-Eh | R/W-0h | R/W-1h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | ILIM2_VTH | R/W | 9h | ILIM2 Threshold
00000b = OutOfRange_0x00 00001b = 110_percent 00010b = 115_percent 00011b = 120_percent 00100b = 125_percent 00101b = 130_percent 00110b = 135_percent 00111b = 140_percent 01000b = 145_percent 01001b = 150_percent 01010b = 155_percent 01011b = 160_percent 01100b = 165_percent 01101b = 170_percent 01110b = 175_percent 01111b = 180_percent 10000b = 185_percent 10001b = 190_percent 10010b = 195_percent 10011b = 200_percent 10100b = 205_percent 10101b = 210_percent 10110b = 215_percent 10111b = 220_percent 11000b = 225_percent 11001b = 230_percent 11010b = 250_percent 11011b = 300_percent 11100b = 350_percent 11101b = 400_percent 11110b = 450_percent 11111b = OutOfRange_0x1F |
| 10-9 | ICRIT_DEG | R/W | 1h | ICRIT deglitch time to trigger PROCHOT
00b = 12us(Min)/14.5us(Typ.)/17us(Max) 01b = 93us(Min)/111us(Typ.)/129us(Max) 10b = 372us(Min)/443us(Typ.)/513us(Max) 11b = 745us(Min)/873us(Typ.)/1000us(Max) |
| 8 | PROCHOT_VINDPM_80_90 | R/W | 0h | Lower threshold of the PROCHOT_VINDPM comparator. When LOWER_PROCHOT_VINDPM=1, the threshold of PROCHOT_VINDPM is determined by this setting. 0b = 83% of VINDPM 1b = 91% of VINDPM |
| 7-2 | VSYS_TH1 | R/W | Eh | VSYS threshold to trigger discharging VBUS in VAP mode.
POR: 6400mV (Eh) Range: 5000mV-11300mV (0h-3Fh) Bit Step: 100mV Offset: 5000mV |
| 1 | INOM_DEG | R/W | 0h | INOM deglitch time
0b = 0.84ms (min)/0.988ms (typ.)/1.14ms (max) 1b = 54ms (min)/64ms (typ.)/73ms (max) |
| 0 | LOWER_PROCHOT_VINDPM | R/W | 1h | Enable lower threshold of PROCHOT_VINDPM comparator:
0b = PROCHOT_VINDPM follows VINDPM REG0x3D setting 1b = PROCHOT_VINDPM is lowered and determined by PROCHOT_VINDPM_80_90 bit setting |
REG0x34_ProchotOption1 is shown in Figure 7-36 and described in Table 7-39.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IDCHG_TH1 | IDCHG_DEG1 | ||||||
| R/W-10h | R/W-1h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PP_VINDPM | PP_CMP | PP_ICRIT | PP_INOM | PP_IDCHG1 | PP_VSYS | PP_BATPRES | PP_ACOK |
| R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | IDCHG_TH1 | R/W | 10h | IDCHG level 1 Threshold 6 bit, range, range 1500A to 33A(5mΩ RSR), step 500mA. There is a 1500mA offset for all code Measure current between SRN and SRP. Trigger when the discharge current is above the threshold. If the value is programmed to 000000b PROCHOT is always triggered. Default: 9500mA or 010000b POR: 9500mA (10h) Range: 1500mA-33000mA (0h-3Fh) Bit Step: 500mA Offset: 1500mA |
| 9-8 | IDCHG_DEG1 | R/W | 1h | IDCHG Deglitch Time
00b = 69ms(min)/78ms(Typ.)/93.6ms(max) 01b = 1.1sec(min)/1.25sec(Typ.)/1.4sec(max) 10b = 4.4sec(min)/5sec(Typ.)/5.6sec(max) 11b = 17.5sec(min)/20sec(Typ.)/22.3sec(max) |
| 7 | PP_VINDPM | R/W | 1h | VINDPM PROCHOT profile enable
0b = Disable 1b = Enable |
| 6 | PP_CMP | R/W | 0h | COMP PROCHOT profile enable
0b = Disable 1b = Enable |
| 5 | PP_ICRIT | R/W | 1h | ICRIT PROCHOT profile enable
0b = Disable 1b = Enable |
| 4 | PP_INOM | R/W | 0h | INOM PROCHOT profile enable
0b = Disable 1b = Enable |
| 3 | PP_IDCHG1 | R/W | 0h | IDCHG1 PROCHOT profile enable
0b = Disable 1b = Enable |
| 2 | PP_VSYS | R/W | 0h | VSYS PROCHOT profile enable
0b = Disable 1b = Enable |
| 1 | PP_BATPRES | R/W | 0h | Battery removal PROCHOT profile enable If PP_BATPRES is enabled in PROCHOT after the battery is removed, PROCHOT pin activates a single falling pulse. 0b = Disable 1b = Enable |
| 0 | PP_ACOK | R/W | 0h | Adapter removal PROCHOT profile enable. If PP_ACOK is enabled in PROCHOT after the adapter is removed, PROCHOT pin activates a single falling pulse. 0b = Disable 1b = Enable |
REG0x35_ADCOption is shown in Figure 7-37 and described in Table 7-40.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADC_RATE | ADC_EN | ADC_SAMPLE | ADC_AVG | ADC_AVG_INIT | RESERVED | ||
| R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EN_ADC_CMPIN | EN_ADC_VBUS | EN_ADC_PSYS | EN_ADC_IIN | RESERVED | EN_ADC_IBAT | EN_ADC_VSYS | EN_ADC_VBAT |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | ADC_RATE | R/W | 1h | ADC conversion type selection Typical conversion time is determined by resolution accuracy. 0b = Continuous update. Cycling set of conversion updates to ADC registers without break. The total period of whole set is determined by the ADC channel enabled count times conversion time for each channel determined by ADC_SAMPLE setting. 1b = One-shot update. Do one set of conversion updates to ADC registers after ADC_START =1. The total period of whole set is determined by the ADC channel enabled count times conversion time for each channel determined by ADC_SAMPLE setting. |
| 14 | ADC_EN | R/W | 0h | ADC conversion enable command. Under one-shot ADC configuration ADC_RATE=0b, After the one-shot update is complete, this bit automatically resets to zero 0b = Idle 1b = Start |
| 13-12 | ADC_SAMPLE | R/W | 1h | ADC sample resolution selection, each channel conversion time is also determined based on resolution.
00b = 15 bits effective resolution(24ms conversion time per channel) 01b = 14 bits effective resolution(12ms conversion time per channel) 10b = 13 bits effective resolution(6ms conversion time per channel) 11b = Reserved |
| 11 | ADC_AVG | R/W | 0h | ADC average control
0b = Single Value 1b = Running average |
| 10 | ADC_AVG_INIT | R/W | 0h | ADC average initial value control
0b = Start average using existing register value 1b = Start average using new ADC conversion |
| 9-8 | RESERVED | R | 0h | Reserved |
| 7 | EN_ADC_CMPIN | R/W | 0h | Enable CMPIN_TR pin Voltage ADC Channel
0b = Disable 1b = Enable |
| 6 | EN_ADC_VBUS | R/W | 0h | Enable VBUS pin Voltage ADC Channel
0b = Disable 1b = Enable |
| 5 | EN_ADC_PSYS | R/W | 0h | Enable PSYS pin Voltage ADC Channel
0b = Disable 1b = Enable |
| 4 | EN_ADC_IIN | R/W | 0h | Enable IIN ADC Channel
0b = Disable 1b = Enable |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | EN_ADC_IBAT | R/W | 0h | Enable ICHG ADC Channel
0b = Disable 1b = Enable |
| 1 | EN_ADC_VSYS | R/W | 0h | Enable VSYS pin Voltage ADC Channel
0b = Disable 1b = Enable |
| 0 | EN_ADC_VBAT | R/W | 0h | Enable SRN pin Voltage ADC Channel
0b = Disable 1b = Enable |
REG0x36_ChargeOption4 is shown in Figure 7-38 and described in Table 7-41.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| VSYS_UVP | EN_DITHER | VSYS_UVP_NO_HICCUP | PP_VBUS_VAP | STAT_VBUS_VAP | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IDCHG_DEG2 | IDCHG_TH2 | PP_IDCHG2 | STAT_IDCHG2 | STAT_PTM | |||
| R/W-1h | R/W-1h | R/W-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | VSYS_UVP | R/W | 0h | VSYS Under Voltage Lock Out After UVP is triggered the charger enters hiccup mode, and then the charger is latched off if the restart fails 7 times in 90s The hiccup mode during the UVP can be disabled by setting VSYS_UVP_NO_HICCUP=1b. 000b = 2.4V 001b = 3.2V 010b = 4.0V 011b = 4.8V 100b = 5.6V 101b = 6.4V 110b = 7.2V 111b = 8.0V |
| 12-11 | EN_DITHER | R/W | 0h | Frequency Dither configuration
00b = Disable 01b = 1X 10b = 2X 11b = 3X |
| 10 | VSYS_UVP_NO_HICCUP | R/W | 0h | Disable VSYS_UVP Hiccup mode operation:
0b = Hiccup Mode Enabled 1b = Hiccup Mode Disabled |
| 9 | PP_VBUS_VAP | R/W | 0h | Enable VBUS_VAP PROCHOT Profile
0b = Disable 1b = Enable |
| 8 | STAT_VBUS_VAP | R | 0h | STAT_VBUS_VAP
0b = Not Triggered 1b = Triggered |
| 7-6 | IDCHG_DEG2 | R/W | 1h | Battery discharge current limit 2 deglitch time
00b = 81us(min)/98us(Typ.)/115us(max) 01b = 1.3ms(min)/1.55ms(Typ.)/1.8ms(max) 10b = 5.2ms(min)/6.25ms(Typ.)/7.3ms(max) 11b = 10.4ms(min)/12.5ms(Typ.)/14.6ms(max) |
| 5-3 | IDCHG_TH2 | R/W | 1h | Battery discharge current limit2 is based on percentage of IDCHG_TH1. Note setting IDCHG_TH2 higher than 40A loses accuracy.
000b = 125%*IDCHG_TH1 001b = 150%*IDCHG_TH1 010b = 175%*IDCHG_TH1 011b = 200%*IDCHG_TH1 100b = 250%*IDCHG_TH1 101b = 300%*IDCHG_TH1 110b = 350%*IDCHG_TH1 111b = 400%*IDCHG_TH1 |
| 2 | PP_IDCHG2 | R/W | 0h | Enable IDCHG_TH2 PROCHOT Profile
0b = Disable 1b = Enable |
| 1 | STAT_IDCHG2 | R | 0h | The status is latched until a read from host.
0b = Not Triggered 1b = Triggered |
| 0 | STAT_PTM | R | 0h | PTM operation status bit monitor
0b = Not Active 1b = Active |
REG0x37_Vmin_Active_Protection is shown in Figure 7-39 and described in Table 7-42.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| VBUS_VAP_TH | DIS_BATOVP_20MA | ||||||
| R/W-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VSYS_TH2 | EN_VSYSTH2_FOLLOW_VSYSTH1 | EN_FRS | |||||
| R/W-9h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | VBUS_VAP_TH | R/W | 0h | VAP Mode2 VBUS /PROCHOT trigger voltage threshold
POR: 3200mV (0h) Range: 3200mV-15900mV (0h-7Fh) Bit Step: 100mV Offset: 3200mV |
| 8 | DIS_BATOVP_20MA | R/W | 0h | Disable BATOVP 20mA discharge current through VSYS pin
0b = Discharge 20mA under BATOVP 1b = Not discharge 20mA under BATOVP |
| 7-2 | VSYS_TH2 | R/W | 9h | VAP Mode2 VBUS /PROCHOT trigger voltage threshold
POR: 5900mV (9h) Range: 5000mV-11300mV (0h-3Fh) Bit Step: 100mV Offset: 5000mV |
| 1 | EN_VSYSTH2_FOLLOW_VSYSTH1 | R/W | 0h | Enable internal VSYS_TH2 follow VSYS_TH1 setting neglecting register VSYS_TH2 setting
0b = Disable 1b = Enable |
| 0 | EN_FRS | R/W | 0h | Fast Role Swap Feature Enable
0b = Disable 1b = Enable |
REG0x3B_OTG_VOLTAGE is shown in Figure 7-40 and described in Table 7-43.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | OTG_VOLTAGE | ||||||
| R-0h | R/W-FAh | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OTG_VOLTAGE | RESERVED | ||||||
| R/W-FAh | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12-2 | OTG_VOLTAGE | R/W | FAh | OTG output voltage regulation: Note: Writing value beyond clamp high/low actually sets register to the clamp high/low value . POR: 5000mV (FAh) Range: 3000mV-38000mV (96h-76Ch) Clamped Low Clamped High Bit Step: 20mV |
| 1-0 | RESERVED | R | 0h | Reserved |
REG0x3C_OTG_CURRENT is shown in Figure 7-41 and described in Table 7-44.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | OTG_CURRENT | ||||||
| R-0h | R/W-78h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OTG_CURRENT | RESERVED | ||||||
| R/W-78h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10-2 | OTG_CURRENT | R/W | 78h | OTG output current limit with 10mΩ Rac current sense: Note: Writing value beyond clamp high/low actually sets register to the clamp high/low value . POR: 3000mA (78h) Range: 100mA-8200mA (4h-148h) Clamped Low Clamped High Bit Step: 25mA |
| 1-0 | RESERVED | R | 0h | Reserved |
REG0x3D_VINDPM is shown in Figure 7-42 and described in Table 7-45.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | VINDPM | ||||||
| R-0h | R/W-A0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VINDPM | RESERVED | ||||||
| R/W-A0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12-2 | VINDPM | R/W | A0h | Input voltage limit: Note: Writing value beyond clamp high/low sets register to the clamp high/low value . POR: 3200mV (A0h) Range: 3200mV-38000mV (A0h-76Ch) Clamped Low Clamped High Bit Step: 20mV |
| 1-0 | RESERVED | R | 0h | Reserved |
REG0x3E_VSYS_MIN is shown in Figure 7-43 and described in Table 7-46.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | VSYS_MIN | ||||||
| R-0h | R/W-528h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VSYS_MIN | |||||||
| R/W-528h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12-0 | VSYS_MIN | R/W | 528h | Minimum system voltage configuration register Note: Writing value beyond clamp high/low sets register to the clamp high/low value . POR: 6600mV (528h) Range: 5000mV-21000mV (3E8h-1068h) Clamped Low Clamped High Bit Step: 5mV Mode: 2s 6600mV Mode: 3s 9200mV POR: 9200mV (730h) Mode: 4s 12300mV POR: 12300mV (99Ch) Mode: 5s 15400mV POR: 15400mV (C08h) |
REG0x3F_IIN_HOST is shown in Figure 7-44 and described in Table 7-47.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | IIN_HOST | ||||||
| R-0h | R/W-C8h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IIN_HOST | RESERVED | ||||||
| R/W-C8h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10-2 | IIN_HOST | R/W | C8h | Maximum input current limit with 10mΩ sense resistor: Note: Writing value beyond clamp high/low sets register to the clamp high/low value . POR: 5000mA (C8h) Range: 400mA-8200mA (10h-148h) Clamped Low Clamped High Bit Step: 25mA |
| 1-0 | RESERVED | R | 0h | Reserved |
REG0x60_AUTOTUNE_READ is shown in Figure 7-45 and described in Table 7-48.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| AUTOTUNE_A | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AUTOTUNE_B | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | AUTOTUNE_A | R | 0h | Phase A inductor time constant L(µH)/DCR(mΩ) value: AUTOTUNE_A= 256-265*L(µH)/DCR(mΩ). When converter shuts off these bits are set back to 0. |
| 7-0 | AUTOTUNE_B | R | 0h | Phase B inductor time constant L(µH)/DCR(mΩ) value: AUTOTUNE_A= 256-265*L(µH)/DCR(mΩ). When converter shuts off these bits are set back to 0. |
REG0x61_AUTOTUNE_FORCE is shown in Figure 7-46 and described in Table 7-49.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| FORCE_AUTOTUNE_A | |||||||
| R/W-C8h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FORCE_AUTOTUNE_B | |||||||
| R/W-C8h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | FORCE_AUTOTUNE_A | R/W | C8h | Force value for phase A inductor time constant L(µH)/DCR(mΩ) : FORCE_AUTOTUNE_A= 256-265*L(µH)/DCR(mΩ). Default 0xC8 refers to 0.211µH/mΩ |
| 7-0 | FORCE_AUTOTUNE_B | R/W | C8h | Force value for phase B inductor time constant L(µH)/DCR(mΩ): FORCE_AUTOTUNE_B= 256-265*L(µH)/DCR(mΩ) Default 0xC8 refers to 0.211µH/mΩ |
REG0x62_GM_ADJUST_FORCE is shown in Figure 7-47 and described in Table 7-50.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| GM_ADJUST | FORCE_UPDATE | RESERVED | |||||
| R-0h | R/W-0h | R-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FORCE_GM_ADJUST | FORCE_GM_ADJUST_EN | FORCE_AUTOTUNE_EN | |||||
| R/W-31h | R/W-0h | R/W-1h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | GM_ADJUST | R | 0h | Auto adaptive adjustment value for inductor DCR. This value is 0 when converter shuts off. If converter starts switching and FORCE_GM_ADJUST_EN=1b then GM_ADJUST=FORCE_GM_ADJUST+1 as fixed value. |
| 9 | FORCE_UPDATE | R/W | 0h | Update FORCE_AUTOTUNE_A, FORCE_AUTOTUNE_B, FORCE_GM_ADJUST value to be effective for inductor DCR current sense. Converter automatically shuts off and restart when this bit is written from 0b to 1b to login new force values. After one time update completes, the converter automatically recovers switching and reset this bit to 0b.
0b = Idle 1b = Update FORCE_AUTOTUNE_A,FORCE_AUTOTUNE_B, FORCE_GM_ADJUST values to converter |
| 8 | RESERVED | R | 0h | Reserved |
| 7-2 | FORCE_GM_ADJUST | R/W | 31h | Force GM adjustment value for inductor DCR: GM_ADJUST= 71.25-272/DCR(mΩ) Default value 0x31 refers to 12.2mΩ |
| 1 | FORCE_GM_ADJUST_EN | R/W | 0h | Enable FORCE_GM_ADJUST effective for inductor DCR current sense. Converter automatically shuts off and restart when FORCE_UPDATE bit is written from 0b to 1b to update these force values. When converter restarts from other reason, as long as this bit is 1b, converter force GM_ADJUST = FORCE_GM_ADJUST+1 as fixed value
0b = Disable FORCE_GM_ADJUST 1b = Enable FORCE_GM_ADJUST |
| 0 | FORCE_AUTOTUNE_EN | R/W | 1h | Enable FORCE_AUTOTUNE_A, FORCE_AUTOTUNE_B effective for inductor DCR current sense. Converter automatically shuts off and restart when FORCE_UPDATE bit is written from 0b to 1b to update these force values. When converter restarts from other reasons, as long as this bit is 1b, converter follow the FORCE_AUTO_TUNE_A/B value and there is no auto calibration at beginning anymore.
0b = Disable FORCE_AUTOTUNE_A,FORCE_AUTOTUNE_B 1b = Enable FORCE_AUTOTUNE_A,FORCE_AUTOTUNE_B |
REG0xFD_VIRTUAL_CONTROL is shown in Figure 7-48 and described in Table 7-51.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EN_AUTO_CHG | RESERVED | EN_OTG | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| REG_RESET | RESERVED | EN_EXTILIM | RESERVED | WD_RST | WDTMR_ADJ | ||
| R/W-0h | R-0h | R/W-1h | R-0h | R/W-0h | R/W-3h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | EN_AUTO_CHG | R/W | 0h | Automatic charge control(recharge and terminate battery charging automatically):
0b = Disable 1b = Enable |
| 14-9 | RESERVED | R | 0h | Reserved |
| 8 | EN_OTG | R/W | 0h | OTG Mode Enable Enable device in OTG mode when EN_OTG pin is HIGH. 0b = Disable 1b = Enable |
| 7 | REG_RESET | R/W | 0h | Reset Registers All the R/W and R registers go back to the default setting except: CHRG_STAT, MODE_STAT, HIDRV1_STAT, LODRV1_STAT, HIDRV2_STAT, LODRV2_STAT 0b = Idle 1b = Reset |
| 6-5 | RESERVED | R | 0h | Reserved |
| 4 | EN_EXTILIM | R/W | 1h | Enable ILIM_HIZ pin to set input current limit
0b = Disable(Input current limit is set by IIN_HOST()) 1b = Enable(Input current limit is set by the lower value of ILIM_HIZ pin and IIN_HOST()) |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | WD_RST | R/W | 0h | Reset watch dog timer control:
0b = Normal 1b = Reset(bit goes back to 0 after timer reset) |
| 1-0 | WDTMR_ADJ | R/W | 3h | WATCHDOG Timer Adjust Set maximum delay between consecutive EC host write of charge voltage or charge current command. If device does not receive a write on the CHARGE_VOLTAGE() or the CHARGE_CURRENT() within the watchdog time period, the charger is suspended by setting the CHARGE_CURRENT() to 0mA. After expiration, the timer resume upon the write of CHARGE_CURRENT(), CHARGE_VOLTAGE() ,WDTMR_ADJ or WD_RST=1b. The charger resume if the values are valid. 00b = Disable 01b = 5 sec 10b = 88 sec 11b = 175 sec |
REG0xFE_Manufacture_ID is shown in Figure 7-49 and described in Table 7-52.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MANUFACTURE_ID | |||||||
| R-40h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0h | Reserved |
| 7-0 | MANUFACTURE_ID | R | 40h | Manufacture ID : 40h |
REG0xFF_Device_ID is shown in Figure 7-50 and described in Table 7-53.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DEVICE_ID | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0h | Reserved |
| 7-0 | DEVICE_ID | R | 0h | Device ID BQ25785: 00 000 000(0h) |