SLUSG46 March   2026 BQ25785

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2578X
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi-dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  System Voltage Maximum Regulation (SYS_MAX)
        6. 7.3.26.6  Battery Overvoltage Protection (BATOVP)
        7. 7.3.26.7  Battery Charge Overcurrent Protection (BATCOC)
        8. 7.3.26.8  Battery Discharge Overcurrent Protection (BATDOC)
        9. 7.3.26.9  BATFET Charge Current Clamp Protection Under LDO Regulation Mode
        10. 7.3.26.10 Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 SMBus Interface
        1. 7.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 7.5.1.2 Timing Diagrams
    6. 7.6 BQ25785 Register Map
    7. 7.7 BQ25785 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Layout Example Reference Top View
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.1 Power-Up Sequence

The device powers up from the higher voltage of VBUS or VBAT through internal power selector. The charger starts up when VBUS exceeds VVBUS_UVLOZ or VBAT exceeds VVBAT_UVLOZ for 5ms. Upon POR (power on reset) the charger resets all the registers to the default state. Another 5ms later, the user registers become accessible to the host. When VBAT> VBAT_UVLO: if VBUS falls below VBUS_UVLO then adapter removal is detected to enter battery only low power mode. When VBAT< VBAT_UVLO: if VBUS falls below VBUS_UVLO then device is off without interface communication and device performs a POR when the VBUS rise is above VBUS_UVLOZ.

Power up sequence when the charger is powered up from VBUS:

  • After VBUS rises above VVBUS_UVLOZ, there is 50ms deglitch time. After this 50ms deglitch time, charger enables REGN_A/B LDOs. CHRG_OK pin goes high and STAT_AC is set to 1b once REGN_A/B voltages ramp up. If EN_LWPWR is set to 0b then the device is in performance mode. REGN_A/B is kept on when there is a battery present before VBUS is plugged in.
  • MODE pin detection is executed after device POR to determine converter topology, converter compensation option and converter switching frequency.
  • VBUS qualification is then executed. During VBUS qualification process, there is a internal 20mA current sink 100ms pulse adding on VBUS pin to verify that the input source is strong enough to pass qualification. During this 100ms, if VVBUS_CONVEN<VBUS <VACOV_RISE, then the charger passes VBUS qualification and proceeds to the next step. However, if VVBUS_UVLOZ < VBUS < VVBUS_CONVEN or VBUS> VACOV_RISE, then the charger fails VBUS qualification, the charger re-qualifies VBUS every 2s. During this 2s, even if VBUS rise up higher than VVBUS_CONVEN, the converter is still shutting down due to failing VBUS qualification at the beginning.
  • During VBUS qualification, Battery cell configuration is read at CELL_BATPRES pin voltage and compared to REGN_A/B to determine cell configuration. The default value of CHARGE_VOLTAGE(), CHARGE_CURRENT(),VRECHG(), VSYS_MIN() and SYSOVP thresholds are loaded respectively. Also IINDPM is detected at ILIM_HIZ pin steady state voltage.
  • After passing the qualification, VBUS ADC is executed one time to read the no-load VBUS voltage and save the value into ADC_VBUS() register.
  • Check voltage between VBUS and ACP_A (VBUS-ACP_A) is below VSC_VBUSACP_FALLING to make sure eFuse or PFETs are fully turned on. If not, hold on converter power up until SC_VBUSACP is not triggered.
  • Normally 226ms after VBUS above VVBUS_CONVEN, converter powers up. If SC_VBUSACP is still triggered then the converter power is up, there can be a wait until this is cleared.

Power up sequence when the charger is powered up from VBAT:

  • If only the battery is present and the voltage is above VVBAT_UVLOZ, the charger wakes up and the BATFET is turned on and connecting the battery to system.
  • MODE pin detection is executed right after device POR to determine converter topology, converter compensation option and converter switching frequency.
  • By default, the charger is in low power mode (EN_LWPWR = 1b) with the lowest quiescent current. The REGN_A/B LDO is turned off by default but when EN_LWPWR=1, the LDO is turned on, the LDO current limit is reduced to 5mA to minimize the quiescent current.
  • The adapter present comparator is activated, to monitor the VBUS voltage.
  • SDA and SDL lines stand by waiting for host commands.
  • The device can move to performance mode by configuring EN_LWPWR = 0b. The host can enable IBAT buffer through setting EN_IBAT=1b to monitor discharge current. The PSYS also can be enabled by the host. CELL_BATPRES pin detection is executed one time when CELL_BATPRES pin is pulled up or REGN_A/B rise up from GND to steady state value. Note that under the battery only low power mode, CELL_BATPRES detection is not executed.
  • In performance mode, the REGN_A/B LDO is always available to provide an accurate reference and gate drive voltage for the converter.