SLUSG46 March   2026 BQ25785

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2578X
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi-dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  System Voltage Maximum Regulation (SYS_MAX)
        6. 7.3.26.6  Battery Overvoltage Protection (BATOVP)
        7. 7.3.26.7  Battery Charge Overcurrent Protection (BATCOC)
        8. 7.3.26.8  Battery Discharge Overcurrent Protection (BATDOC)
        9. 7.3.26.9  BATFET Charge Current Clamp Protection Under LDO Regulation Mode
        10. 7.3.26.10 Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 SMBus Interface
        1. 7.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 7.5.1.2 Timing Diagrams
    6. 7.6 BQ25785 Register Map
    7. 7.7 BQ25785 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Layout Example Reference Top View
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.4.1 Layout Guidelines

Proper layout of the components to minimize high frequency current path loop (see Section 8.4.2) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. The following table is a PCB layout priority list for proper layout.

Table 8-7 PCB Layout Guidelines
RULES COMPONENTS FUNCTION IMPACT GUIDELINES
1 PCB layer stack up Thermal, efficiency, signal integrity Multi- layer PCB is suggested. Allocate at least one ground layer. The BQ2_A, Q2_B577XEVM uses a 6-layer PCB (top layer, ground layer, signal layer and bottom layer).
2 CBUS, RAC_A, RAC_B, Q1_A, Q1_B, Q2_A, Q2_B Input loop High frequency noise, ripple VBUS capacitors, RAC_A, RAC_B, Q1_A, Q1_B and Q2_A, Q2_B form two small loops 1 and 2. Put the capacitors on the same side. Connect the capacitors with large copper to reduce the parasitic resistance. Move part of CBUS to the other side of PCB for high density design. After RAC_A, RAC_B before Q1_A, Q1_B and Q2_A, Q2_B power stage recommend to put 10µF(0603/0805 package)+10nF+1nF(0402 package) decoupling capacitors as close as possible to IC to decoupling switching loop high frequency noise.
3 RAC_A, RAC_B, Q1_A, Q1_B, L1, Q4 Current path Efficiency The current path from VBUS to VSYS, through RAC_A, RAC_B, Q1_A, Q1_B, L1, Q4, has low impedance. Pay attention to via resistance if the vias are not on the same side. The number of vias can be estimated as 1Ato 2A per via for a 10mil via with 1oz copper thickness.
4 CSYS, Q3, Q4 Output loop High frequency noise, ripple VSYS capacitors, Q3 and Q4 form a small loop 3. Put the capacitors on the same side. Connect the capacitors with large copper to reduce the parasitic resistance. Move part of CSYS to the other side of PCB for high density design.
5 QBAT, RSR Current path Efficiency, battery voltage detection Place QBAT and RSR near the battery terminal. The current path from VBAT to VSYS, through RSR and QBAT, has low impedance. Pay attention to via resistance if the vias are not on the same side. The device detects the battery voltage through SRN near battery terminal.
6 Q1_A, Q1_B, Q2_A, Q2_B, L1, Q3, Q4 Power stage Thermal, efficiency Place Q1_A and Q2_A, Q1_B and Q2_B, L1, Q3 and Q4 next to each other. Allow enough copper area for thermal dissipation. The copper area is suggested to be 2x to 4x of the pad size. Multiple thermal vias can be used to connect more copper layers together and dissipate more heat.
7 RAC_A, RAC_B, RSR Current sense Regulation accuracy Use Kelvin-sensing technique for RAC_A, RAC_B and RSR current sense resistors. Connect the current sense RAC_A, RAC_B to the center of the pads, and run current sense traces as differential pairs.
8 Small capacitors IC bypass caps Noise, jittering, ripple Place VBUS capacitor, VCC capacitor, REGN capacitors near the IC.
9 BTST capacitors HS gate drive High frequency noise, ripple Place HS MOSFET boost strap circuit capacitor close to IC and on the same side of PCB board. Capacitors SW1_A/SW1_B/2 nodes are recommended to use wide copper polygon to connect to power stage and capacitors BTST1_A/BTST1_B/BTST2 node are recommended to use at least 8mil trace to connected to IC BTST1_A/BTST1_B/BTST2 pins.
10 Ground partition Measurement accuracy, regulation accuracy, jitters, ripple Separate analog ground(AGND) and power grounds(PGND) is preferred. PGND must be used for all power stage related ground net. AGND must be used for all sensing, compensation and control network ground for example ACP_A/ACN_A/ACP_B/ACN_B/CMPIN_TR/CMPOUT/IADPT/IBAT/PSYS. Connect all analog grounds to a dedicated low-impedance copper plane, which is tied to the power ground underneath the IC exposed pad. If possible, use dedicated AGND traces. Connect analog ground and power ground together using power pad as the single ground connection point.