SLUSG46 March   2026 BQ25785

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2578X
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi-dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  System Voltage Maximum Regulation (SYS_MAX)
        6. 7.3.26.6  Battery Overvoltage Protection (BATOVP)
        7. 7.3.26.7  Battery Charge Overcurrent Protection (BATCOC)
        8. 7.3.26.8  Battery Discharge Overcurrent Protection (BATDOC)
        9. 7.3.26.9  BATFET Charge Current Clamp Protection Under LDO Regulation Mode
        10. 7.3.26.10 Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 SMBus Interface
        1. 7.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 7.5.1.2 Timing Diagrams
    6. 7.6 BQ25785 Register Map
    7. 7.7 BQ25785 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Layout Example Reference Top View
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)

The charger monitors total system power. During forward mode, the input adapter powers the system. During reverse OTG mode and battery only discharge scenario, the battery powers the system and VBUS output. The ratio of PSYS pin output current and total system power, KPSYS, can be programmed in PSYS_RATIO register bit with default 1μA/W. The input and charge sense resistors (RAC and RSR) are selected in RSNS_RAC bit and RSNS_RSR bit. If PSYS_CONFIG=00b then PSYS voltage can be calculated with Equation 2, where IIN_A/IIN_B >0 when the charger is in forward charging and IIN_A/IIN_B <0 when charger is in OTG operation; where IBAT<0 when the battery is in charging and IBAT>0 when battery is discharging.

Equation 2. VPSYS =RPSYS·KPSYS(VACP_A·IIN_A+VACP_B·IIN_B+VSYS·IBAT)

For proper PSYS functionality, RAC practical value is limited to 10mΩ or 5mΩ and must be consistent with RSNS_RAC register setting; RSR practical value is limited to 5mΩ or 2mΩ and must be consistent with RSNS_RSR register setting.

The charger can block IBAT contribution to above equation by setting PSYS_CONFIG =01b in forward mode and block IBUS contribution to above equation by setting PSYS_OTG_IDCHG=1b.

To minimize the quiescent current, the PSYS function is disabled by default PSYS_CONFIG = 11b.

Table 7-9 PSYS Configuration Table
CASE #

PSYS_CONFIG BITS

PSYS_OTG_IDCHG

BITS

FORWARD MODE PSYS

CONFIGURATION

OTG

MODE PSYS

CONFIGURATION

100b0bPSYS=PBUS+PBATPSYS=PBUS+PBAT
200b1bPSYS=PBUS+PBATPSYS=PBAT
301b0bPSYS=PBUSPSYS=0
401b1bPSYS=PBUSPSYS=0
511bXbPSYS=0(Disabled)PSYS=0(Disabled)