SLVA275C january   2010  – may 2023 UCD9081

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware
    1. 2.1 Package: RHB (S-PQFP-N32), 32-Pin Plastic Quad Flatpack
    2. 2.2 Hardware and Pinout
    3. 2.3 Detailed Pin Descriptions
      1. 2.3.1 RST
      2. 2.3.2 SDA
      3. 2.3.3 SCL
      4. 2.3.4 ADDRx
      5. 2.3.5 ROSC
  5. 3Software
    1. 3.1 Data File Format
    2. 3.2 I2C Transactions
    3. 3.3 Device Version
    4. 3.4 Checksum
    5. 3.5 Sample Configuration Data File
      1. 3.5.1 Factory Default
      2. 3.5.2 EVM Default Configuration
    6. 3.6 I2C Write and Read Transaction Formats
      1. 3.6.1 I2C Write Transaction
      2. 3.6.2 I2C Read Transaction
    7. 3.7 Pseudo I2C Write and Read Transactions
      1. 3.7.1 UCD9081 I2C Transactions for Writing User Data and PARAMS
      2. 3.7.2 UCD9081 I2C Transactions for Reading User Data and PARAMS
  6. 4User Configuration
    1. 4.1 Configuration Parameter Memory Map
    2. 4.2 Configuration Parameter Detail
      1. 4.2.1  GpDir
      2. 4.2.2  NegateEnablePolarity
      3. 4.2.3  SeqEventPending
      4. 4.2.4  SequenceEventParameters
      5. 4.2.5  SequenceEventLink
      6. 4.2.6  SequenceEventData
      7. 4.2.7  DependencyMasks
      8. 4.2.8  UnderVoltageThresholds
      9. 4.2.9  OverVoltageThresholds
      10. 4.2.10 RampTime
      11. 4.2.11 OutOfRegulationWidth
      12. 4.2.12 UnsequenceTime
      13. 4.2.13 EnablePolarity
      14. 4.2.14 SaveRailLog
      15. 4.2.15 ReferenceSelect
      16. 4.2.16 LastUnusedSeq
      17. 4.2.17 IgnoreGlitchAlarms
      18. 4.2.18 IgnoreFlashErrorLog
      19. 4.2.19 Checksum
  7. 5Additional Considerations
    1. 5.1 Embedded Application
    2. 5.2 Timing
      1. 5.2.1 UCD9081 Startup
      2. 5.2.2 Clock Stretching After Flash Erase
      3. 5.2.3 Bit Timeout
      4. 5.2.4 Byte or Transaction Timeout
  8. 6References
  9. 7Revision History

5.2.3 Bit Timeout

The UCD9081 enforces a maximum bit timeout period of 1/f SCL(MIN) (100 µs) for the bit cases described in the following list. This bit period must be met or else the UCD9081 may exit a transaction, causing a NACK to occur. For the bit cases not described in the following list, the byte timeout applies as described in Section 5.2.4.

  • START bit (Figure 5-3): SCL must fall within 100 µs of SDA falling.
    GUID-91FE7940-E0EE-4F46-95AE-98E5D3F02DC3-low.gifFigure 5-3 START Bit Requirement
  • Eighth data bit of write command (Figure 5-4): SCL must fall within 100 µs of SCL rising.
    GUID-CC0242A7-6925-49DF-B5E7-FE312728442A-low.gifFigure 5-4 Eighth Bit of Write Command Requirements
  • Read/write bit of slave address command (Figure 5-5): SCL must fall within 100 µs of SCL rising.
    GUID-1CA14C5A-5614-4ADF-BE0F-3616D1154805-low.gifFigure 5-5 Read/Write Bit Requirements
  • Acknowledge bit (Figure 5-6): Acknowledge (ACK) or no-acknowledge (NACK) occurs on the ninth rising edge of SCL during each byte. After ACK or NACK, SCL must fall within 100 µs of SCL rising.
    GUID-0DF33A40-4F4D-475A-BB43-1F074E841936-low.gifFigure 5-6 Acknowledge Bit Requirements