SLVAE30E February 2021 – March 2021 TPS1H000-Q1 , TPS1H100-Q1 , TPS1H200A-Q1 , TPS1HA08-Q1 , TPS25200-Q1 , TPS27S100 , TPS2H000-Q1 , TPS2H160-Q1 , TPS2HB16-Q1 , TPS2HB35-Q1 , TPS2HB50-Q1 , TPS4H000-Q1 , TPS4H160-Q1

- Trademarks
- 1Introduction
- 2Driving Resistive Loads
- 3Driving Capacitive Loads
- 4Driving Inductive Loads
- 5Driving LED Loads
- 6Appendix
- 7References
- 8Revision History

The large thermal dissipation that a High Side
Switch sustains during capacitive inrush can exceed the average power dissipation of the
device calculated in Power Dissipation
Calculation. This leads to
relibaility concerns if device junction temperatures rise above T_{j(Max)} and
possibly cause the device to go into Over Temperature Shutdown.

For average power consumption, we had estimated junction temperature as in Equation 4. Capacitive inrush events, however, are not steady-state conditions and are short in duration. A high-side switch may be able to tolerate higher-than-average power dissipation for short periods during inrush events due to the input-dependent thermal impedance.

Transient thermal impedance is typically modeled
via a Foster RC network, shown in Figure 3-13. This model links the
high-side switch junction temperature T_{J} to ambient temperature T_{A} and
the response of the thermal RC network to power dissipated in the device P_{DIS}.
The thermal impedance values in the model are strongly dependent on device construction and
packaging. Z_{ΘJA} is defined as in Equation 25.

Equation 28.

This model shows us that short bursts of power
have less effect on the junction temperature if the period is much less than the RC time
constant, acting as a high-pass filter. For long periods of time, the thermal capacitances
block the power and all the power passes through the thermal resistances
R_{1,2,3..n}. The sum of these thermal resistances in the model is
R_{ΘJA}, which is specified in the device data sheets. The modeled response to a
fast power transient is compared to a steady-state power dissipation in Figure 3-13.

During capacitive inrush, Z_{ΘJA},
P_{DIS}, and T_{J} are functions of time during, as shown in Figure 3-13. Time is on a logarithmic
scale, and Z_{ΘJA} is the time dependent thermal impedance of the device (between
junction and ambient air)*. *Z_{ΘJA} follows an exponential decay according to
the time constants of the Foster model for a particular device.

Z_{ΘJA} is monotonically increasing during
the inrush period, Δt, but total power dissipated in the device is dropping linearly due to
current limiting. The peak power dissipation *I _{LIM}·V_{SUP}* occurs
at the beginning of this period, while Z

This converse relationship causes junction temperature to peak at approximately half of the
inrush period, or at Δt/2. This holds true as long the inrush period Δt is less than the
effective thermal time constant of the device, or before Z_{ΘJA} plots flatten out.
This is around 500 s for most high-side switches.

Mathematically, junction temperature is the convolution of Z_{ΘJA} and P_{DIS},
which are both time variant, shown in Equation 26. Evaluating this
convolution to find ΔT_{j} is exceedingly difficult, and is best left to simulators
like PSPICE if the device has a thermal-enabled model available.

Equation 26.

For design purposes, we are mainly concerned with finding TEquation 27.

In Equation 27, ZFigures for transient thermal impedance Z_{ΘJA} are located in Appendix
A and provided for each TI
high-side switch listed in Table 3-1.

Equation 27 is accurate to within ±10% of PSPICE simulation results for T_{J(Max)},
but only for inrush times Δt < ~500 s, or the point at which the Z_{ΘJA} curve
flattens. Beyond this point, this approximation begins to undershoot as peak temperature occurs
later than Δt/2. A more advanced thermal simulation with PSPICE, Simulink, or another
modeling tool should be used at that point.

This procedure can be repeated for multi-channel
devices using the transient thermal data Z_{ΘJA} for 2 or 4-Ch ON. However, this
data should only be used for situations where both channels turn on simulatenously and the
loading conditions are identical.

Adding on to our examples for TPS2H160-Q1, we can
estimate T_{J(Max)} during capacitive inrush. In this example, a single channel
drives a 470-µF capacitive load, current limit I_{LIM} is set to 1 A, supply voltage
is 24 V, and the ambient temperature is T_{A} = 25°C.

From Equation 18, we found the inrush
period lasts Δt = 11.28 ms. Referencing the data for TPS2H160-Q1 in Appendix
A, we can draw a line at Δt
= 11.28 ms as in Figure 3-16 to find the values of
R_{ΘJA} at half the inrush period Δt since we are only driving on one channel,
Z_{ΘJA}(Δt/2) = 5.4°C/W.

Current limiting is active during the inrush
period and is responsible for significant power dissipation in the high-side switch. This is
because current limiting is achieved through control of the FET R_{ON}.
R_{ON} must be forced up to several orders of magnitude higher than the data sheet
specification a the beginning of inrush, which leads to high I^{2}R losses in the
FET channel.

Once the device turns on the FET, V_{DS}
across the fet is initially V_{SUP} and reduces to nearly 0 V once the capacitor
load is charged. This initial point is where the peak power dissipation occurs. In our
example with TPS2H160-Q1, we had set ILIM = 1 A, so the peak power is 24 V·1 A = 24W. We
can now calculate T_{J(MAX)} during inrush by substituting our values for
V_{SUP}, I_{LIM}, T_{A}, and Z_{ΘJA(Δt/2)} into Equation 27, shown in Equation 28.

Equation 28.

From Equation 28, we
find that the TAs this is an estimate and operating conditions
may vary from the design point, it is recommended to allow for sufficient headroom between
T_{J(Max)} and 150°C. Not properly limiting T_{J} may trigger
over-temperature shutdown and reduce both reliability and device lifetime.

In addition to keeping T_{J} < 150°C,
it is recommended to keep ΔT_{J} < T_{SW}, where T_{SW} = 60°C to
prevent thermal swing shutdown during inrush. As the highest temperature will occur in the
FET junction during inrush, designing for ΔT_{J} < T_{SW} guarantees
thermal swing shutdown will not be triggered during inrush. Since T_{FET}
T_{CON} are strongly time-depenedent on loading conditions over inrush,
ΔT_{J} could also potentially be larger than T_{SW} without triggering
thermal swing shutdown.

For the most accurate thermal results, it is
strongly recommended to use thermal-enabled PSPICE models for TI's high-side switches which
model T_{J}, T_{CON}, and thermal shutdown. For more information on
simulating device thermals in PSPICE, please see Using PSpice Simulator to Model Thermal Behavior in
TI’s Smart High-Side Switches.