SLVAEP5A April   2020  – June 2021 LM3668 , TPS63000 , TPS63000-Q1 , TPS63001 , TPS63002 , TPS63010 , TPS63011 , TPS63020 , TPS63020-Q1 , TPS63021 , TPS63024 , TPS630241 , TPS630242 , TPS630250 , TPS630251 , TPS630252 , TPS63027 , TPS63030 , TPS63031 , TPS63036 , TPS63050 , TPS63051 , TPS63060 , TPS63061 , TPS63070 , TPS63802 , TPS63805 , TPS63806 , TPS63810 , TPS63811 , TPS63900 , TPS63901


  1.   Trademarks
  2. 1Introduction
  3. 2EMI Sources
  4. 3Device Optimization
  5. 4Migration from two-layer to four-layer board
  6. 5Additional Capacitors to a Chassis Ground
  7. 6Summary
  8. 7References
  9. 8Revision History

EMI Sources

GUID-56F76D86-3A8C-4FBC-9FB0-3314F4FD5BEA-low.gif Figure 2-1 EMI Sources in Non-inverting Buck-boost Converter

Figure 2-1 highlights the main sources of EMI in a non-inverting buck-boost converter.

The first EMI source is the hot loop located between input capacitor (CIN) and SW2. The second loop responsible for EMI is the loop located between output capacitor (COUT) and SW3. The loops occurrence differs dependent on the converter operating mode. In Figure 2-1, the left loop exists during buck mode operation while the right most loop, during boost mode operation. Due to the switching logic, these loops will have high rates of change in current over time (di/dt). Taking into account the equivalent series inductance (ESL) of a capacitor and the equation of voltage over inductor Equation 1, it can be seen that these hot loops can give rise to unwanted voltages (vL).

Equation 1. GUID-C82482B3-0A41-40CA-AA8B-06B3C48FC370-low.gif

The switching nodes L1 and L2 are another EMI source. Depending on the operation mode, L1 for buck and L2 for boost, these nodes experience high changes in voltage over time (dv/dt). A change in voltage can give rise to undesired currents in a capacitor as shown by Equation 2. Keeping in mind that capacitances can develop between inductor windings, the occurrence of parasitic currents (i2C) is possible.

Equation 2. GUID-6A86C0EF-09E7-485F-9203-D5A0D27795F0-low.gif

Besides the parasitic capacitance of the inductor, another capacitance also exists between the node and the ground layer. This capacitance is described by Equation 3 and it is strongly influenced by the distance (d) between the layer on which the node is located and the closest ground layer as well as by the area of the parallel plates (A). ε0 and εr are the permittivity of free space (ε0=8.85 pF/m) and the relative permittivity of the medium between the two plates.

Equation 3. GUID-41DDCEC0-3891-46D1-BC13-6C61F9D93C49-low.gif

The following sections will introduce tested solutions that reduce radiations. The proposed solutions are accompanied by measurements that prove their effectiveness. The measurements were conducted in accordance to the CISPR 16-2-3 standards and regulations referenced in Section 7.