SLVSGY2A October   2023  – October 2025 TPS2HCS10-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Version A Package
    2. 5.2 Pinout - Version A
    3. 5.3 Version B Package
    4. 5.4 Pinout - Version B
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Overcurrent Protection
          1. 8.3.1.1.1 Inrush Period - Overcurrent Protection
          2. 8.3.1.1.2 Overcurrent Protection - Steady State Operation
          3. 8.3.1.1.3 Programmable Fuse Protection
          4. 8.3.1.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
          5. 8.3.1.1.5 Auto Retry and Latch-Off Behavior
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 Integrated ADC
        2. 8.3.2.2 Digital Current Sense Output
        3. 8.3.2.3 Output Voltage Measurement
        4. 8.3.2.4 MOSFET Temperature Measurement
        5. 8.3.2.5 Drain-to-Source Voltage (VDS) Measurement
        6. 8.3.2.6 VBB Voltage Measurement
        7. 8.3.2.7 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.7.1 Measurement with Channel Output (FET) Enabled
          2. 8.3.2.7.2 Detection with Channel Output Disabled
      3. 8.3.3 Parallel Mode Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 Output Control
      3. 8.4.3 SPI Mode Operation
      4. 8.4.4 Fault Reporting
      5. 8.4.5 SLEEP
      6. 8.4.6 CONFIG/ACTIVE
      7. 8.4.7 LIMP_HOME State (Version A only)
      8. 8.4.8 Battery Supply Input (VBB) Under-Voltage
      9. 8.4.9 LOW POWER MODE (LPM) States
        1. 8.4.9.1 MANUAL_LPM State
        2. 8.4.9.2 AUTO_LPM State
    5. 8.5 TPS2HCS10-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.3 Parallel Mode Operation

When the PARALLEL_12 bit is set to 1, the device supports a parallel mode where the outputs of the device can be connected together externally to operate the device as a single channel device. This reduces the RON approximately by half and increases the continuous output current by approximately 2x.

When setting the PARALLEL_12 bit, both channels must be off in order for it to take effect. To confirm if the PARALLEL_12 bit has taken effect, the DEV_CONFIG register can be read to verify the PARALLEL_12 bit is set to 1.

The following sections cover the different configurations and behaviors specific to the parallel mode of the device. If any function or feature is not described in the followings sections, the device will operate the same as in single channel operation for that function or feature.

Channel Control in Parallel Mode

In parallel mode, channel control in the ACTIVE state is set only through the CH1_ON bit in the SW_STATE register for TPS2HCS10A-Q1. For TPS2HCS10B-Q1, channel control in ACTIVE state is set only through the DI1 pin. For LIMP_HOME state, channel control is set only through CH1_LH_IN bits only in the DEV_CONFIG register.

Fault Reporting - Parallel Mode

In parallel mode, if a fault on either or both channels, the fault flags for both channels will assert for the respective fault.

Diagnostics - Parallel Mode

In parallel mode, the ADC diagnostics (ISNS, VSNS, VBBSNS, VDS_SNS, and TSNS) are available for both channels. These diagnostics can be enabled or disabled on a per channel basis through the respective CHx_CONFIG registers.

To enter KSNS2 operation (or also known as OL_ON_EN_CHx = 1 mode), the output current must be below 2x IENTRY_OL_ON before the OL_ON_EN_CH1 bit is set to 1. If the current is not below 2x IENTRY_OL_ON, the KSNS2 operation will not be entered and the KSNS1 operation will still be active. If the channel is operating with KSNS2 and the output current increases above 2x IEXIT_OL_ON, the device will automatically transition out of KSNS2 to KSNS1 where the OL_ON_EN_CH1 bit will be reset to 0 and the full MOSFET is active. If the current falls below 2x IENTRY_OL_ON again then the OL_ON_EN_CH1 bit needs to be set back to 1 to transition to KSNS2 operation again. The system can manually exit KSNS2 operation by writing OL_ON_EN_CH1 = 0. When measuring the output current through the integrated ADC in KSNS2 operation, the system should continue to monitor the OL_ON_EN_CH1 = 1 bit to ensure the device is still in KSNS2 operation when the output current measurement is read.

Off state open load detection and off state short to battery detection settings are set by the CH1_CONFIG register only. The device will only enable the circuitry on channel 1 to detect off state open load and the off state short to battery.

Inrush Period - Overcurrent Protection in Parallel Mode

In parallel mode, the overcurrent protection in the optional inrush period is set by the ILIM_CONFIG_CH1 register only. Either of the two capacitive charging modes, no capacitive charging or current regulation, can be used in parallel mode and is set by the CAP_CHRG_CH1 bits. The duration for the inrush period is set by INRUSH_DURATION_CH1. The value for the capacitive charging is set by the INRUSH_LIMIT_CH1 bits and the effective value for the entire device for parallel operation will be approximately double the INRUSH_LIMIT_CH1 setting.

The overcurrent protection and thermal shutdown protection in both channels will be enabled for the two capacitive charging modes. For the no capacitive charging mode, if the output current through either channel goes above the INRUSH_LIMIT_CH1 setting then both channels will be turned off. For both capacitive charging modes, if either channel has a thermal shutdown fault, both channels will be turned off.

See Table 8-3below for more details on how the device can be configured for the overcurrent protection in the optional inrush period.

Table 8-3 Inrush Period Overcurrent Protection Configuration Methods for Parallel Mode
Capacitive Charging Mode (CAP_CHRG_CH1) Duration Set By Value Set By Effective Typical Value When PARALLEL_12 = 1
00 INRUSH_DURATION_CH1 [2:0] INRUSH_LIMIT_CH1 [3:0] 2x INRUSH_LIMIT_CH1 [3:0]
10 INRUSH_DURATION_CH1 [2:0] INRUSH_LIMIT_CH1 [3:0] 2x INRUSH_LIMIT_CH1 [3:0]

Steady State - Overcurrent Protection in Parallel Mode

In parallel mode, the immediate shutdown overcurrent protection (IOCP) in the steady state operation is set by the ILIMIT_SET_CH1 bits in the ILIM_CONFIG_CH1 register only. The effective value for the entire device for parallel operation will be approximately double the ILIMIT_SET_CH1 setting.

The overcurrent protection and thermal shutdown protection in both channels will be enabled in steady state operation. If the output current through either channel goes above the ILIMIT_SET_CH1 setting then both channels will be turned off.

Note:

The max ILIMIT_SET_CH1 value that is supported for parallel mode is 20A. If CAP_CHRG_CH1 = 00, the max INRUSH_LIMIT_CH1 value that is supported for parallel mode is 20A.

Steady State - I2T Protection in Parallel Mode

In parallel mode, the I2T protection is set by the I2T_CONFIG_CH1 register only. The value for INOM for the I2T is set by the NOM_CUR_CH1 bits and the effective value for the entire device for parallel operation will be approximately double the NOM_CUR_CH1 setting. The value for the I2T threshold is set by the I2T_TRIP_CH1 bits and the effective value for the entire device for the parallel operation is approximately quadruple the I2T_TRIP_CH1 setting. The value for the ISWCL is set by the ISWCL_CH1 bits and the effective value for the entire device for the parallel operation is approximately double the ISWCL_CH1 setting.

Enabling of I2T in parallel mode is done only through the I2T_EN_CH1 bit in the ILIM_CONFIG_CH1 register.

For I2T accumulation, only the current sense for channel 1 is used. If the I2T_TRIP_CH1 value is exceeded for channel 1 then both channels will be turned off.

MANUAL_LPM - Parallel Mode

In parallel mode, the MANUAL_LPM is entered through the MANUAL_LPM_ENTRY bit. The device operates the same as in single channel operation as described in the MANUAL_LPM section with the following exceptions:

  • For TPS2HCS10A-Q1, the device only monitors the AUTO_LPM_EXIT_CH1 setting when coming out of MANUAL_LPM to determine if the channel needs to be turned on when in active state if not already enabled. AUTO_LPM_EXIT_CH2 setting will be ignored.
  • The device monitors the output current for both channels to determine when the device will exit the MANUAL_LPM state. If either of the channels output current exceeds the IEXIT_LPM_MAN thresholds, the device will exit the MANUAL_LPM state. For the correct operation, MAN_LPM_EXIT_CURR_CH1 and MAN_LPM_EXIT_CURR_CH2 settings need to be set to the same value. The effective value for the entire device for the parallel operation is approximately double the MAN_LPM_EXIT_CURR_CHx settings.
  • For TPS2HCS10B-Q1, the device only monitors changes in the DI1 pin to exit MANUAL_LPM.

AUTO_LPM - Parallel Mode

In parallel mode, the AUTO_LPM is entered AUTO_LPM_ENTRY bit is set to 1. The device operates the same as in single channel operation as described in the AUTO_LPM section with the following exceptions:

  • For TPS2HCS10A-Q1, the device will only monitor AUTO_LPM_EXIT_CH1 to exit AUTO_LPM and turn on the channels if they are not already enabled. AUTO_LPM_EXIT_CH2 setting will be ignored.
  • The device monitors the output current for both channels to determine when the device should exit the AUTO_LPM state. If either of the channels output current exceeds the IEXIT_LPM_AUTO threshold, the device will exit the AUTO_LPM state. The effective value for the entire device for the parallel operation is approximately double the IEXIT_LPM_AUTO value.
  • For TPS2HCS10B-Q1, the device will only monitor changes in the DI1 pin to exit AUTO_LPM.

PWM - Parallel Mode

In parallel mode, the PWM settings will be set by the PWM_CH1 register only. The PWM_SHIFT_DIS bit will be ignored as both channels will turn on at the same time. Enabling of PWM for parallel mode is done through the PWM_EN_CH1 bit.

RON - Parallel Mode

The RON for each channel varies slightly from each other and can cause a small load mismatch. This is specified in the electrical characteristics through the ΔRON parameter.

Layout Recommendations - Parallel Mode

In parallel mode, the routing of the output channels is important to avoid any additional load mismatch. The output traces should be symmetrical to avoid any extra resistance which can cause uneven current draw through the output channels.