SLVSGY2A October   2023  – October 2025 TPS2HCS10-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 5.1 Version A Package
    2. 5.2 Pinout - Version A
    3. 5.3 Version B Package
    4. 5.4 Pinout - Version B
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Overcurrent Protection
          1. 8.3.1.1.1 Inrush Period - Overcurrent Protection
          2. 8.3.1.1.2 Overcurrent Protection - Steady State Operation
          3. 8.3.1.1.3 Programmable Fuse Protection
          4. 8.3.1.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
          5. 8.3.1.1.5 Auto Retry and Latch-Off Behavior
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 Integrated ADC
        2. 8.3.2.2 Digital Current Sense Output
        3. 8.3.2.3 Output Voltage Measurement
        4. 8.3.2.4 MOSFET Temperature Measurement
        5. 8.3.2.5 Drain-to-Source Voltage (VDS) Measurement
        6. 8.3.2.6 VBB Voltage Measurement
        7. 8.3.2.7 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.7.1 Measurement with Channel Output (FET) Enabled
          2. 8.3.2.7.2 Detection with Channel Output Disabled
      3. 8.3.3 Parallel Mode Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 Output Control
      3. 8.4.3 SPI Mode Operation
      4. 8.4.4 Fault Reporting
      5. 8.4.5 SLEEP
      6. 8.4.6 CONFIG/ACTIVE
      7. 8.4.7 LIMP_HOME State (Version A only)
      8. 8.4.8 Battery Supply Input (VBB) Under-Voltage
      9. 8.4.9 LOW POWER MODE (LPM) States
        1. 8.4.9.1 MANUAL_LPM State
        2. 8.4.9.2 AUTO_LPM State
    5. 8.5 TPS2HCS10-Q1 Registers
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

CONFIG/ACTIVE

The CONFIG/ACTIVE state is where the device stays during normal operation when the outputs are OFF (CONFIG) or ON (ACTIVE). The difference between the two is that in the CONFIG state (with the outputs OFF) all of the registers can be configured. In the ACTIVE state with the outputs ON, the parallel configuration of the channel cannot be changed (PARALLEL_12 bit in the DEV_CONFIG register). The configuration registers (especially ones needed to successfully enable the channel) are expected to be written to before the outputs can be turned ON, when transitioning from the SLEEP state (and all the registers are lost). However, the configuration registers are retained while in the LPM state and so the device does not need to be reconfigured while tranisitioning from the LPM state to the ACTIVE state. The quiescent current draw from VBB, (IQ,VBB) and VDD, (IQ,VDD) is higher than in the other states to support the load and device diagnostics. SPI communication and diagnostics checks are fully supported in this state.

The device can be transitioned into the CONFIG state from the SLEEP state by the CSN pin going low (a dummy SPI command serves this purpose). The device completes the transition through all initializations and functional safety checks. The device transitions to and from the LIMP HOME state depending on the internal SPI watchdog monitor and the status of the LHI input pin. The device can transition into and out of the LPM state by a write to the LPM register.

In the CONFIG state, the device utilizes a gate to source pulldown to achieve the configured slew rate when the channel is enabled and disabled. As a result, when the channel is off there is a 1µA bias path to VOUT which creates a 1µA leakage current to VOUT. If there is no load on the output this can cause the output to float up. To reduce the open load VOUT voltage, the RSHRT_VBB pulldown resistor can be enabled to reduce the output voltage to low levels. The RSHRT_VBB pulldown resistor can be enabled through the OL_SVBB_EN_CHx [1:0] bits in the CHx_CONFIG registers. In SLEEP and LPM states, to achieve the lowest IQ the device instead utilizes a gate to ground pulldown so the 1µA bias path doesn't exist in these states.