SLVSGY2A October   2023  – October 2025 TPS2HCS10-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Version A Package
    2. 5.2 Pinout - Version A
    3. 5.3 Version B Package
    4. 5.4 Pinout - Version B
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Overcurrent Protection
          1. 8.3.1.1.1 Inrush Period - Overcurrent Protection
          2. 8.3.1.1.2 Overcurrent Protection - Steady State Operation
          3. 8.3.1.1.3 Programmable Fuse Protection
          4. 8.3.1.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
          5. 8.3.1.1.5 Auto Retry and Latch-Off Behavior
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 Integrated ADC
        2. 8.3.2.2 Digital Current Sense Output
        3. 8.3.2.3 Output Voltage Measurement
        4. 8.3.2.4 MOSFET Temperature Measurement
        5. 8.3.2.5 Drain-to-Source Voltage (VDS) Measurement
        6. 8.3.2.6 VBB Voltage Measurement
        7. 8.3.2.7 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.7.1 Measurement with Channel Output (FET) Enabled
          2. 8.3.2.7.2 Detection with Channel Output Disabled
      3. 8.3.3 Parallel Mode Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 Output Control
      3. 8.4.3 SPI Mode Operation
      4. 8.4.4 Fault Reporting
      5. 8.4.5 SLEEP
      6. 8.4.6 CONFIG/ACTIVE
      7. 8.4.7 LIMP_HOME State (Version A only)
      8. 8.4.8 Battery Supply Input (VBB) Under-Voltage
      9. 8.4.9 LOW POWER MODE (LPM) States
        1. 8.4.9.1 MANUAL_LPM State
        2. 8.4.9.2 AUTO_LPM State
    5. 8.5 TPS2HCS10-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
8.3.1.1.5 Auto Retry and Latch-Off Behavior

When a thermal shutdown or an overcurrent protection fault occurs, the channel with the fault will either auto-retry or latch off based on the LATCH_CHx bit setting in the CHx_CONFIG registers. Depending on the CAP_CHRG_CHx settings the auto retry response will behave differently.

Note, in LIMP_HOME state the device will continuously retry regardless of the LATCH_CHx setting if the channel is configured to be ON in LIMP_HOME state through the CHx_LH_IN bits. The retry behavior in LIMP_HOME state will follow the below sections depending on how the CAP_CHRG_CHx bits are configured.

Auto Retry Behavior - No Capacitive Charging Mode (CAP_CHRG_CHx = 00)

If CAP_CHRG_CHx = 00 and LATCH_CHx = 0 and a short circuit event occurs, after the channel turns off and tRETRY expires the device will retry in the inrush period with the IOCP level set through the INRUSH_LIMIT_CHx [3:0] bits. The INRUSH_DURATION_CHx [2:0] still sets the duration of the inrush period. Figure 8-8 showcases this hot short case that occur in steady state operation. Starting into a short in the inrush period results in the same retry behavior as a hot short in steady state except the first initial overcurrent shutdown level will be determined by the INRUSH_LIMIT_CHx [3:0].

TPS2HCS10-Q1 Hot Short During Steady State Operation with CAP_CHRG_CHx = 00, Auto-Retry (LATCH_CHx = 0) Figure 8-8 Hot Short During Steady State Operation with CAP_CHRG_CHx = 00, Auto-Retry (LATCH_CHx = 0)

Latch-Off Behavior - No Capacitive Charging Mode (CAP_CHRG_CHx = 00)

If LATCH_CHx = 1 and CAP_CHRG_CHx = 00 and the IOCP level is exceeded, the device will latch-off and will not retry until the CHx_ON bit (version A) is toggled or the DIx pin (version B) is toggled or the LATCH_CHx bit is toggled. Upon resetting the latch either through an output toggle or through the LATCH_CHx bit toggle, the channel will start up into the inrush period if configured. Figure 8-9 below shows the latch behavior if a hot short circuit occurs during steady state operation with LATCH_CHx = 1. Figure 8-10 shows the latch behavior if the channel starts into a short circuit event in the inrush period.

TPS2HCS10-Q1 Hot Short During Steady State Operation with CAP_CHRG_CHx = 00, Latch-Off (LATCH_CHx = 1) Figure 8-9 Hot Short During Steady State Operation with CAP_CHRG_CHx = 00, Latch-Off (LATCH_CHx = 1)
TPS2HCS10-Q1 Start into a Short Circuit Event with CAP_CHRG_CHx = 00, Latch-Off (LATCH_CHx = 1) Figure 8-10 Start into a Short Circuit Event with CAP_CHRG_CHx = 00, Latch-Off (LATCH_CHx = 1)

Auto Retry Behavior - Current Limit Regulation Charging Mode (CAP_CHRG_CHx = 10)

If a short circuit event occurs in steady state operation with CAP_CHRG_CHx = 10 and LATCH_CHx = 0, after the channel turns off and tRETRY expires the device will retry into the inrush period with the current limit regulation (ICL_REG) set through the INRUSH_LIMIT_CHx [3:0] bits. Figure 8-11 shows a hot short event that occurs in steady state operation with CAP_CHRG_CHx = 10 and LATCH_CHx = 0. Figure 8-12 shows the auto-retry behavior if the channel starts into a short circuit event in the inrush period.

TPS2HCS10-Q1 Hot Short During Steady State Operation with CAP_CHRG_CHx = 10 and Auto-Retry (LATCH_CHx = 0) Figure 8-11 Hot Short During Steady State Operation with CAP_CHRG_CHx = 10 and Auto-Retry (LATCH_CHx = 0)
TPS2HCS10-Q1 Start into a Short Circuit Event with CAP_CHRG_CHx = 10 and Auto-Retry (LATCH_CHx = 0) Figure 8-12 Start into a Short Circuit Event with CAP_CHRG_CHx = 10 and Auto-Retry (LATCH_CHx = 0)

Latch-Off Behavior - Current Limit Regulation Capactive Charging Mode (CAP_CHRG_CHx = 10)

If LATCH_CHx = 1 and CAP_CHRG_CHx = 10 and the IOCP level is exceeded, the device will latch-off and will not retry until the CHx_ON bit (version A) is toggled or the DIx pin (version B) is toggled or the LATCH_CHx bit is toggled. Upon resetting the latch either through an output toggle or through the LATCH_CHx bit toggle, the channel will start up into the inrush period if configured. Figure 8-13 below shows the latch behavior if a hot short circuit occurs during steady state operation with LATCH_CHx = 1. Figure 8-14 shows the latch behavior if the channel starts into a short circuit event in the inrush period.

TPS2HCS10-Q1 Hot Short During Steady State Operation with CAP_CHRG_CHx = 10, Latch-Off (LATCH_CHx = 1) Figure 8-13 Hot Short During Steady State Operation with CAP_CHRG_CHx = 10, Latch-Off (LATCH_CHx = 1)
TPS2HCS10-Q1 Start into a Short Circuit Event with CAP_CHRG_CHx = 10, Latch-Off (LATCH_CHx = 1) Figure 8-14 Start into a Short Circuit Event with CAP_CHRG_CHx = 10, Latch-Off (LATCH_CHx = 1)