SLVSGY2A October   2023  – October 2025 TPS2HCS10-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Version A Package
    2. 5.2 Pinout - Version A
    3. 5.3 Version B Package
    4. 5.4 Pinout - Version B
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Overcurrent Protection
          1. 8.3.1.1.1 Inrush Period - Overcurrent Protection
          2. 8.3.1.1.2 Overcurrent Protection - Steady State Operation
          3. 8.3.1.1.3 Programmable Fuse Protection
          4. 8.3.1.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
          5. 8.3.1.1.5 Auto Retry and Latch-Off Behavior
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 Integrated ADC
        2. 8.3.2.2 Digital Current Sense Output
        3. 8.3.2.3 Output Voltage Measurement
        4. 8.3.2.4 MOSFET Temperature Measurement
        5. 8.3.2.5 Drain-to-Source Voltage (VDS) Measurement
        6. 8.3.2.6 VBB Voltage Measurement
        7. 8.3.2.7 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.7.1 Measurement with Channel Output (FET) Enabled
          2. 8.3.2.7.2 Detection with Channel Output Disabled
      3. 8.3.3 Parallel Mode Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 Output Control
      3. 8.4.3 SPI Mode Operation
      4. 8.4.4 Fault Reporting
      5. 8.4.5 SLEEP
      6. 8.4.6 CONFIG/ACTIVE
      7. 8.4.7 LIMP_HOME State (Version A only)
      8. 8.4.8 Battery Supply Input (VBB) Under-Voltage
      9. 8.4.9 LOW POWER MODE (LPM) States
        1. 8.4.9.1 MANUAL_LPM State
        2. 8.4.9.2 AUTO_LPM State
    5. 8.5 TPS2HCS10-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.4.9 LOW POWER MODE (LPM) States

The device offers two low power mode (LPM) states where the device can remain on but the device operates in a low quiescent current (IQ) state to extend battery life. The device offers a manual LPM (MANUAL_LPM) state which can be entered through a SPI write to the LPM register and an automatic LPM (AUTO_LPM) state which can be entered automatically if the output current in the enabled channels is below a certain threshold for tSTBY_LPM_AUTO.

When the device is in either LPM state, SPI writes and reads are only available to the LPM register. In either LPM state, the device can continue to pass SPI data to successive devices in a daisy chain configuration and the status bits in the SDO frame can still be read. When the device transitions in and out of LPM, the fault bits in the SDO frame will update to alert the system the device has exited LPM mode.

A valid VDD voltage greater than VDD_UVLOF is required for the device to remain in either of the LPM states. If the VDD voltage is removed in either LPM states the device will transition to the SLEEP state which in turn disables the outputs and clears the registers.

In MANUAL_LPM state, the device disables all diagnostics as well as the watchdog timer and I2T protection to help reduce the IQ of the device. Once the device exits MANUAL_LPM, the diagnostics which were enabled prior to LPM entry will automatically be re-enabled. I2T protection and the watchdog timer will also be re-enabled after LPM exit. For AUTO_LPM state, the system must first disable the watchdog timer and all ADC diagnostics except ISNS before the device can transition into the AUTO_LPM state. The device will automatically disable the I2T protection and ISNS for AUTO_LPM state and will re-enable these functions when the device exits the AUTO_LPM state to the ACTIVE state. In terms of protection, short-circuit protection remains enabled in the both the LPM states. Different short circuit thresholds are used in the LPM states compared to the short circuit thresholds in ACTIVE state.

When in either of the LPM states, the device automatically responds to load current increases by transitioning to active state. If the current increase is too high the device will trip its short circuit protection. For MANUAL_LPM state, the device provides a wake signal to the microcontroller (which is in sleep mode) to wake the system up through the FLT / WAKE_SIG pin for either load increase scenario. For the AUTO_LPM state, only a load increase above the LPM short-circuit threshold (ISCP_AUTO) will trigger the FLT / WAKE_SIG pin to be pulled low. If a load increase in AUTO_LPM is above the exit threshold (IEXIT_LPM_AUTO) but below the ISCP_LPM_AUTO threshold, the device will not pull the FLT / WAKE_SIG pin low. For both LPM states, the device will only signal an overcurrent protection fault if the overcurrent is confirmed in the ACTIVE state as well.

If needed, the system can manually wake up the device from the LPM states through different SPI writes depending on the LPM state that the device is in. If LHI goes high in either of the LPM states, the device will exit LPM and will transition to ACTIVE state and then to LIMP_HOME state.

Table 8-11 below highlights some of the major differences between the two low power modes. For more information on how each LPM state operates, see the below sections on the MANUAL_LPM and AUTO_LPM states.

Table 8-11 LPM Characteristics
Mode Type Entry Method Specification Description Typical Unit
MANUAL_LPM Write 1 to LPM bit in LPM register IQ,VBB,LPM_MAN Both channels enabled 6.42 μA
IQ,VDD,LPM_MAN Both channels enabled 15.6 μA
RON,LPM_MAN RON in MANUAL_LPM 36 mΩ
IEXIT_LPM_MAN IEXIT_LPM_MAN_CHx = 00 0.5 A
IEXIT_LPM_MAN_CHx = 01 0.625
IEXIT_LPM_MAN_CHx = 10 0.15
IEXIT_LPM_MAN_CHx = 11 0.325
ISCP_LPM_MAN short-circuit threshold in MANUAL_LPM 4 A
AUTO_LPM Automatic entry if AUTO_LPM_ENTRY =1 IQ,VBB,LPM_AUTO Both channels enabled 11.6 μA
IQ,VDD,LPM_AUTO Both channels enabled 15.6 μA
RON,LPM_AUTO RON in AUTO_LPM 11.3 mΩ
tSTBY_LPM_AUTO standby time before entry into AUTO_LPM if IOUTx < IENTRY_LPM_AUTO 20 ms
IENTRY_LPM_AUTO IOUTx current to enter AUTO_LPM 0.95 A
IEXIT_LPM_AUTO IOUTx current to exit AUTO_LPM 1.05 A
ISCP_LPM_AUTO short-circuit threshold in AUTO_LPM 13.7 A