SLVSHS0A March   2025  – October 2025 TPS482H85-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics_24V
    8. 6.8 Switching Characteristics_48V
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Current and Voltage Conventions
      2. 7.3.2 Accurate Current Sense
      3. 7.3.3 Adjustable Current Limit
      4. 7.3.4 Inductive-Load Switching-Off Clamp
      5. 7.3.5 Fault Detection and Reporting
        1. 7.3.5.1 Diagnostic Enable Function
        2. 7.3.5.2 Multiplexing of Current Sense
        3. 7.3.5.3 FLT Reporting
        4. 7.3.5.4 Fault Table
      6. 7.3.6 Full Diagnostics
        1. 7.3.6.1 Short-to-GND and Overload Detection
        2. 7.3.6.2 Open-Load Detection
          1. 7.3.6.2.1 Channel On
          2. 7.3.6.2.2 Channel Off
        3. 7.3.6.3 Short-to-Battery Detection
        4. 7.3.6.4 Reverse-Polarity and Battery Protection
        5. 7.3.6.5 Thermal Fault Detection
          1. 7.3.6.5.1 Thermal Protection Behavior
      7. 7.3.7 Full Protections
        1. 7.3.7.1 UVLO Protection
        2. 7.3.7.2 Loss of GND Protection
        3. 7.3.7.3 Loss of Power Supply Protection
        4. 7.3.7.4 Loss of VDD
        5. 7.3.7.5 Reverse Current Protection
        6. 7.3.7.6 Protection for MCU I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operational Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
        1. 8.4.2.1 Without a GND Network
        2. 8.4.2.2 With a GND Network
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.9 Typical Characteristics

TPS482H85-Q1 VBB Undervoltage Lockout Falling
 
Figure 6-1 VBB Undervoltage Lockout Falling
TPS482H85-Q1 Output Leakage Current Per Channel
 
Figure 6-3 Output Leakage Current Per Channel
TPS482H85-Q1 Current Sense Signal, VBB = 8V
 
Figure 6-5 Current Sense Signal, VBB = 8V
TPS482H85-Q1 Current Sense Signal, VBB = 48V
 
Figure 6-7 Current Sense Signal, VBB = 48V
TPS482H85-Q1 Open-Load Detection Voltage
 
Figure 6-9 Open-Load Detection Voltage
TPS482H85-Q1 VOUT Rising Slew Rate
 
Figure 6-11 VOUT Rising Slew Rate
TPS482H85-Q1 Channel Turn-On Time
 
Figure 6-13 Channel Turn-On Time
TPS482H85-Q1 Current Limit Regulation Level: 1A
 
Figure 6-15 Current Limit Regulation Level: 1A
TPS482H85-Q1 Current Limit Regulation Level: 3A
 
Figure 6-17 Current Limit Regulation Level: 3A
TPS482H85-Q1 Current Limit Regulation Level: 5A
 
Figure 6-19 Current Limit Regulation Level: 5A
TPS482H85-Q1 Single Pulse Energy, VBB = 32V, TJ_start = 125°C
 
Figure 6-21 Single Pulse Energy, VBB = 32V, TJ_start = 125°C
TPS482H85-Q1 ZϴJA (transient thermal impedance) with JEDEC standard 2s2p PCB layout, 4 Vias below VBB Pad
TA = 105 °C 
Figure 6-23 ZϴJA (transient thermal impedance) with JEDEC standard 2s2p PCB layout, 4 Vias below VBB Pad
TPS482H85-Q1 Standby Current
 
Figure 6-2 Standby Current
TPS482H85-Q1 On-Resistance Per Channel
 
Figure 6-4 On-Resistance Per Channel
TPS482H85-Q1 Current Sense Signal, VBB = 24V
 
Figure 6-6 Current Sense Signal, VBB = 24V
TPS482H85-Q1 Input Voltage Low-Level and High-Level for EN Pins
 
Figure 6-8 Input Voltage Low-Level and High-Level for EN Pins
TPS482H85-Q1 Channel Turn-On (tDR) and Turn-Off (tDF) Delay Time
 
Figure 6-10 Channel Turn-On (tDR) and Turn-Off (tDF) Delay Time
TPS482H85-Q1 VOUT Falling Slew Rate
 
Figure 6-12 VOUT Falling Slew Rate
TPS482H85-Q1 Channel Turn-Off Time
 
Figure 6-14 Channel Turn-Off Time
TPS482H85-Q1 Current Limit Regulation Level: 2A
 
Figure 6-16 Current Limit Regulation Level: 2A
TPS482H85-Q1 Current Limit Regulation Level: 4A
 
Figure 6-18 Current Limit Regulation Level: 4A
TPS482H85-Q1 Current Limit Regulation Level: 6A
 
Figure 6-20 Current Limit Regulation Level: 6A
TPS482H85-Q1 Single Pulse Energy, VBB = 54V, TJ_start = 125°C
 
Figure 6-22 Single Pulse Energy, VBB = 54V, TJ_start = 125°C