SLVSHS0A March   2025  – October 2025 TPS482H85-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics_24V
    8. 6.8 Switching Characteristics_48V
    9. 6.9 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Current and Voltage Conventions
      2. 7.3.2 Accurate Current Sense
      3. 7.3.3 Adjustable Current Limit
      4. 7.3.4 Inductive-Load Switching-Off Clamp
      5. 7.3.5 Fault Detection and Reporting
        1. 7.3.5.1 Diagnostic Enable Function
        2. 7.3.5.2 Multiplexing of Current Sense
        3. 7.3.5.3 FLT Reporting
        4. 7.3.5.4 Fault Table
      6. 7.3.6 Full Diagnostics
        1. 7.3.6.1 Short-to-GND and Overload Detection
        2. 7.3.6.2 Open-Load Detection
          1. 7.3.6.2.1 Channel On
          2. 7.3.6.2.2 Channel Off
        3. 7.3.6.3 Short-to-Battery Detection
        4. 7.3.6.4 Reverse-Polarity and Battery Protection
        5. 7.3.6.5 Thermal Fault Detection
          1. 7.3.6.5.1 Thermal Protection Behavior
      7. 7.3.7 Full Protections
        1. 7.3.7.1 UVLO Protection
        2. 7.3.7.2 Loss of GND Protection
        3. 7.3.7.3 Loss of Power Supply Protection
        4. 7.3.7.4 Loss of VDD
        5. 7.3.7.5 Reverse Current Protection
        6. 7.3.7.6 Protection for MCU I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operational Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
        1. 8.4.2.1 Without a GND Network
        2. 8.4.2.2 With a GND Network
  10. Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
Thermal Protection Behavior

The thermal protection behavior can be split up into three categories of events that can happen. Figure 7-14 shows each of these categories.

  1. Relative thermal shutdown: The device is enabled into an overcurrent event. The output current rises up to the IILIM level and the FLT goes low. With this large amount of current going through the junction temperature of the FET increases rapidly with respect to the controller temperature. When the power FET temperature rises TREL amount above the controller junction temperature ΔT = TFET – TCON > TREL, the device shuts down. For auto-retry version, after tRETRY, the part tries to restart. The latch version requires EN to be toggled to re-enable the channel. The FLT pin is asserted until the fault condition is cleared. The first plot in Figure 7-14 shows the relative thermal shutdown behavior for the auto-retry version.
  2. Absolute thermal shutdown: the device is still enabled in an overcurrent event. However, in this case the junction temperature rises up and hits an absolute reference temperature, TABS, and then shuts down. For auto-retry version, the device does not recover until both TJ < TABS – Thys and the tRETRY timer has expired. For latch version, toggling EN is required to re-enable the channel. The second plot in Figure 7-14 shows the absolute thermal shutdown behavior for the auto-retry version.
  3. Latch behavior: the device is enabled into an overcurrent event. The DIAG_EN pin is high so that diagnostics can be monitored on SNS and FLT. For the latched version of the device, if the part shuts down due to a thermal fault, either relative thermal shutdown or absolute thermal shutdown, the device does not enable the channel until the EN pin is toggled. The third plot in Figure 7-14 shows the relative thermal shutdown behavior for the variants with LATCH pin when LATCH pin is HIGH.
TPS482H85-Q1 Thermal BehaviorFigure 7-14 Thermal Behavior