Proper PCB design and layout is important in high-current, fast-switching regulator circuits (with high current and voltage slew rates) to achieve reliable device operation and design robustness. Furthermore, the EMI performance of the regulator depends to a large extent on PCB layout.

The high-frequency power loop of a buck regulator power stage is denoted in red in Figure 9-14. The topological architecture of a buck regulator means that particularly high di/dt current flows in the components of the shaded loop, and reducing the parasitic inductance of this loop by minimizing the effective loop area becomes mandatory (Figure 9-14).

Figure 9-14 Input Current Loop

The following list summarizes the essential guidelines for PCB layout and component placement to optimize DC/DC regulator performance, including thermals and EMI signature. Figure 9-15 shows a recommended layout of the device with optimized placement and routing of the power-stage and small-signal components.

• Place the ceramic input capacitors as close as possible to the input power pins: The VIN and PGND pins are close together (with a gap in between to increase clearance), thus simplifying input capacitor placement.
  • Use low-ESR ceramic capacitors with X7R or X7S dielectric from VIN to PGND. Place an 0402 or 0603 capacitor close to VIN for high-frequency bypass as shown in Figure 9-15. Use additional 1206 or 1210 capacitors for bulk capacitance.
  • Ground return paths for both the input and output capacitors must consist of localized top-side planes that connect to the PGND pins.
• Use a solid ground plane on the PCB layer beneath the top layer with the IC: This plane acts as a noise shield and a heat dissipation path. Using the PCB layer directly below the IC minimizes the magnetic field associated with the currents in the switching loops, thus reducing parasitic inductance and switch voltage overshoot and ringing. Use numerous thermal vias near VIN and PGND for heatsinking to the inner copper planes.
• Make the VIN, VOUT, and GND bus connections as wide as possible: These paths must be wide and direct as possible to reduce any voltage drops on the input or output paths of the regulator, thus maximizing efficiency.
• Locate the buck inductor close to the SW pin: Use a short, wide connection trace from the regulator SW pin to the inductor. At the same time, minimize the length (and area) of this high-dv/dt surface to help reduce capacitive coupling and radiated EMI. Connect the dotted terminal of the inductor to the SW pins
• Place the VCC and BOOT capacitors close to the respective pins: The VCC and BOOT capacitors represent the supplies for the low-side and high-side MOSFET gate drivers, respectively, and thus carry high-frequency currents. Locate C_VCC close to the VCC pin and place a GND via at the return terminal to connect to the GND plane and thus back to IC GND at the exposed pad. Connect C_BOOT close to the CBOOT and SW pins.
• Provide enough PCB area for proper heatsinking: Use sufficient copper area to achieve a low thermal impedance commensurate with the maximum load current and ambient temperature conditions. Provide adequate heatsinking for the device to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed pad (GND) of the package to the PCB ground plane. If the PCB has multiple copper layers, connect these thermal vias to inner-layer ground planes. Make the top and bottom PCB layers preferably with two-ounce copper thickness (and no less than one ounce).