SLVSIO7 July   2026 LM5192

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Related Products
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for the Serial Control Bus
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulators (VCC, VDDA)
      3. 7.3.3  Enable (EN)
      4. 7.3.4  Switching Frequency
      5. 7.3.5  Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Soft Start
      7. 7.3.7  Output Voltage
      8. 7.3.8  Minimum Controllable On-Time
      9. 7.3.9  Dual Loop Architecture
        1. 7.3.9.1 Voltage Loop Error Amplifier
        2. 7.3.9.2 Current Loop Error Amplifier
      10. 7.3.10 Programmable ILIM
      11. 7.3.11 IOUT Monitor
      12. 7.3.12 Cable Drop Compensation
      13. 7.3.13 Slope Compensation
      14. 7.3.14 Shunt Current Sensing
      15. 7.3.15 Hiccup Mode Current Limiting
      16. 7.3.16 Device Configuration (CNFG)
      17. 7.3.17 Pulse Frequency Modulation (PFM) / Synchronization
      18. 7.3.18 Out-of-Audio Operation
      19. 7.3.19 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Ready Mode
      4. 7.4.4 Active Mode
      5. 7.4.5 Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
      2. 7.5.2 Clock Stretching
      3. 7.5.3 Data Transfer Formats
      4. 7.5.4 Single READ from a Defined Register Address
      5. 7.5.5 Sequential READ Starting from a Defined Register Address
      6. 7.5.6 Single WRITE to a Defined Register Address
      7. 7.5.7 Sequential WRITE Starting at a Defined Register Address
  9. LM5192 Registers
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 EMI Filter
    2. 9.2 Typical Application
      1. 9.2.1 High Efficiency, Wide Input, 400kHz, Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Buck Inductor
          3. 9.2.1.2.3 Current-Sense Resistance
          4. 9.2.1.2.4 Output Capacitors
          5. 9.2.1.2.5 Input Capacitors
          6. 9.2.1.2.6 Compensation Components
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
Compensation Components

Select compensation components for a stable control loop using the procedure outlined as follows.

  1. Based on a specified loop gain crossover frequency, fC, of 40kHz, use Equation 31 to calculate RCOMP, assuming an effective output capacitance of 62µF. Select a standard value for RCOMP of 7.68kΩ. VREF is VOUT/10 if VSTEP is 10mV. VREF is VOUT/20 if VSTEP is 20mV.
    Equation 31. R C O M P = 2 × π × f C × V O U T V R E F × R S × G C S g m × C O U T = 2 × π × 40 k H z × 12 V 1.2 V × 5 m Ω × 10 1000 µ S × 62 µ F = 7.79 k Ω  
  2. To provide adequate phase boost at crossover while also allowing a fast settling time during a load or line transient, select CCOMP to place a zero at the higher (1) one tenth of the crossover frequency, or (2) the load pole. Select a standard value for CCOMP of 4.7nF .
    Equation 32. C C O M P = 10 2 × π × f C × R C O M P = 10 2 × π × 40 k H z × 7.68 k Ω = 5.18 n F
  3. Calculate CHF to create a pole at the ESR zero and to attenuate high-frequency noise on the COMP pin. CBW is the bandwidth-limiting capacitance of the error amplifier. 1pF CHF can be ignored in this design. However, in noisy environments, especially at high VIN and high load currents, additional capacitance can help filter out the noise.
    Equation 33. C H F = 1 2 × π × f E S R × R C O M P - C B W = 1 2 × π × 642 k H z × 7.68 k Ω - 15 p F = 17 p F
Note: Set a fast loop with high RCOMP and low CCOMP values to improve the response when recovering from operation in dropout.