STATUS_CML is shown in Figure 7-53 and described in Table 7-73.
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Write Transaction: Write Byte
Read Transaction: Read Byte
Data Format: unsigned binary (1 byte)
NVM Back-up: No
Updates: On-the-fly The STATUS_CML command returns one byte with contents relating to communications, logic, and memory as follows. The status bits remain latched even after the fault or warning condition is resolved. The bits can be cleared by:
- CLEAR_FAULTS command
- Writing 1b to the target bit
- Toggling the ON_OFF_CONFIG mechanism of the rail
- Power cycle to reset the device
The STS_CML bit in STATUS_BYTE represents an ORing of the bits in this command. When any of the event occurs that sets a bit in this command, the STS_CML bit is also set. Similarly, if all of the bits in this command are cleared, STS_CML is also cleared.
All bits which can trigger SMB_ALERT# have a corresponding mask bit in the SMBALERT_MASK command.
Table 7-73 STATUS_CML Field Descriptions| Bit | Field | Type | Reset | Description |
|---|
| 7 | IVC | R/W1C | 0h | This latched bit is set when an invalid command is detected and the device responds as follows:- NACK the unsupported command code and all data bytes
- Ignore the received command code and any received data
- Set the STS_CML bit in STATUS_BYTE
- Set the IVC bit in STATUS_CML
- 0h = No invalid or unsupported command.
- 1h = Invalid or unsupported command received.
|
| 6 | IVD | R/W1C | 0h | This latched bit is set when invalid or unsupported data is detected and the device responds as follows:- NACK the invalid or unsupported data bytes
- Ignore the received command code and any received data
- Set the STS_CML bit in STATUS_BYTE
- Set the IVD bit in STATUS_CML
- 0h = No invalid or unsupported data.
- 1h = Invalid or unsupported data received.
|
| 5 | PEC_FAIL | R/W1C | 0h | |
| 4 | MEM | R/W1C | 0h | This latched bit is set when a fault with the internal memory is detected. The source of the fault could be one of the following sources:- Parity check failure during or after STORE_USER_ALL.
- During reset RESTORE (i.e. EEPROM restore at boot-up), either a mismatch between the EEPROM contents and the register contents OR a failure to pass parity checks.
- When the user issues a RESTORE_USER_ALL command, a failure to pass parity checks.
- Failure during the EEPROM programming sequence.
- 0h = No Memory faults.
- 1h = Memory fault detected.
|
| 3 | RESERVED | R | 0h | |
| 2 | RESERVED | R | 0h | |
| 1 | OTH_COMM | R/W1C | 0h | This latched bit is set if a communication fault other than the ones covered by bits [7:5] is detected. The source of the fault could be one of the following sources:- SMBus Clock Low Timeout.
- Failure to communicate with the power-stage through the internal interface.
- 0h = No other communication fault.
- 1h = Other communication fault detected.
|
| 0 | RESERVED | R | 0h | |