The ADS1278QML-SP requires a clock input for operation. The individual converters of the ADS1278QML-SP operate from the same clock input. At the maximum data rate, the clock input can be either 27MHz or 13.5MHz for Low-Power mode, or 27MHz or 5.4MHz for Low-Speed mode, determined by the setting of the CLKDIV input. For High-Speed mode, the maximum CLK input frequency is 32.768MHz. For High-Resolution mode, the maximum CLK input frequency is 27MHz. The selection of the external clock frequency (f_CLK) does not affect the resolution of the ADS1278QML-SP. Use of a slower f_CLK can reduce the power consumption of an external clock buffer. The output data rate scales with clock frequency, down to a minimum clock frequency of f_CLK = 100kHz. Table 6-5 summarizes the ratio of the clock input frequency (f_CLK) to data rate (f_DATA), maximum data rate and corresponding maximum clock input for the four operating modes.

As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible, and using a 50Ω series resistor placed close to the source end, often helps.