The ADS1278QML-SP has three power supplies: AVDD, DVDD, and IOVDD. AVDD is the analog supply that powers the modulator, DVDD is the digital supply that powers the digital core, and IOVDD is the digital I/O power supply. The IOVDD and DVDD power supplies can be tied together if desired (1.8V). To achieve rated performance, the power supplies must be bypassed with 0.1μF and 10μF capacitors placed as close as possible to the supply pins. A single 10μF ceramic capacitor can be substituted in place of the two capacitors.

Figure 7-3 shows the start-up sequence of the ADS1278QML-SP. At power-on, bring up the DVDD supply first, followed by IOVDD and then AVDD. Check the power-supply sequence for proper order, including the ramp rate of each supply. DVDD and IOVDD can be sequenced at the same time if the supplies are tied together. Each supply has an internal reset circuit whose outputs are summed together to generate a global power-on reset. After the supplies have exceeded the reset thresholds, 2¹⁸ f_CLK cycles are counted before the converter initiates the conversion process. Following the CLK cycles, the data for 129 conversions are suppressed by the ADS1278QML-SP to allow output of fully-settled data. In SPI protocol, DRDY is held high during this interval. In frame-sync protocol, DOUT is forced to zero. The power supplies must be applied before any analog or digital pin is driven. For consistent performance, assert SYNC after device power-on when data first appear.