SLVSKW2 January   2026 ADS1278QML-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Quality Conformance Inspection
    7. 5.7 Timing Requirements: SPI Format
    8. 5.8 Timing Requirements: Frame-Sync Format
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Sampling Aperture Matching
      2. 6.3.2  Frequency Response
        1. 6.3.2.1 High-Speed, Low-Power, And Low-Speed Modes
        2. 6.3.2.2 High-Resolution Mode
      3. 6.3.3  Phase Response
      4. 6.3.4  Settling Time
      5. 6.3.5  Data Format
      6. 6.3.6  Analog Inputs (AINP, AINN)
      7. 6.3.7  Voltage Reference Inputs (VREFP, VREFN)
      8. 6.3.8  Clock Input (CLK)
      9. 6.3.9  Mode Selection (MODE)
      10. 6.3.10 Synchronization (SYNC)
      11. 6.3.11 Power-Down ( PWDN)
      12. 6.3.12 Format[2:0]
      13. 6.3.13 Serial Interface Protocols
      14. 6.3.14 SPI Serial Interface
        1. 6.3.14.1 SCLK
        2. 6.3.14.2 DRDY/FSYNC (SPI Format)
        3. 6.3.14.3 DOUT
        4. 6.3.14.4 DIN
      15. 6.3.15 Frame-Sync Serial Interface
        1. 6.3.15.1 SCLK
        2. 6.3.15.2 DRDY/FSYNC (Frame-Sync Format)
        3. 6.3.15.3 DOUT
        4. 6.3.15.4 DIN
      16. 6.3.16 DOUT Modes
        1. 6.3.16.1 TDM Mode
        2. 6.3.16.2 TDM Mode, Fixed-Position Data
        3. 6.3.16.3 TDM Mode, Dynamic Position Data
        4. 6.3.16.4 Discrete Data Output Mode
      17. 6.3.17 Daisy-Chaining
      18. 6.3.18 Modulator Output
      19. 6.3.19 Pin Test Using Test[1:0] Inputs
      20. 6.3.20 VCOM Output
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2 Detailed Design Procedure

To obtain the specified performance from the ADS1278QML-SP, the following layout and component guidelines must be considered.

  1. Power Supplies: The device requires three power supplies for operation: DVDD, IOVDD, and AVDD. The allowed range for DVDD is 1.65V to 1.95V; the range of IOVDD is 1.65V to 3.6V; AVDD is restricted to 4.75V to 5V. For all supplies, use a 10μF tantalum capacitor, bypassed with a 0.1μF ceramic capacitor, placed close to the device pins. Alternatively, a single 10μF ceramic capacitor can be used. The supplies must be relatively free of noise and must not be shared with devices that produce voltage spikes (such as relays, LED display drivers, and more). If a switching power-supply source is used, the voltage ripple must be low (less than 2mV) and the switching frequency outside the passband of the converter.
  2. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter.
  3. Digital Inputs: Source-terminate the digital inputs to the device with 50Ω series resistors. The resistors must be placed close to the driving end of digital source (oscillator, logic gates, DSP, and more) This placement helps to reduce ringing on the digital lines (ringing can lead to degraded ADC performance).
  4. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk.
  5. Reference Inputs: Use a minimum 10μF tantalum with a 0.1μF ceramic capacitor directly across the reference inputs, VREFP and VREFN. The reference input must be driven by a low-impedance source. For best performance, the reference must have less than 3μVRMS in-band noise. For references with noise higher than this level, external reference filtering can be necessary.
  6. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true differential driver or transformer (ac applications) can be used for this purpose. Route the analog inputs tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks. A 1nF to 10nF capacitor must be used directly across the analog input pins, AINP and AINN. A low-k dielectric (such as COG or film type) must be used to maintain low THD. Capacitors from each analog input to ground can be used. The capacitors must be no larger than 1/10 the size of the difference capacitor (typically 100pF) to preserve the ac common-mode performance.
  7. Component Placement: Place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. This layout is particularly important for small-value ceramic capacitors. Larger (bulk) decoupling capacitors can be located farther from the device than the smaller ceramic capacitors.