SLVSKW2 January   2026 ADS1278QML-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Quality Conformance Inspection
    7. 5.7 Timing Requirements: SPI Format
    8. 5.8 Timing Requirements: Frame-Sync Format
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Sampling Aperture Matching
      2. 6.3.2  Frequency Response
        1. 6.3.2.1 High-Speed, Low-Power, And Low-Speed Modes
        2. 6.3.2.2 High-Resolution Mode
      3. 6.3.3  Phase Response
      4. 6.3.4  Settling Time
      5. 6.3.5  Data Format
      6. 6.3.6  Analog Inputs (AINP, AINN)
      7. 6.3.7  Voltage Reference Inputs (VREFP, VREFN)
      8. 6.3.8  Clock Input (CLK)
      9. 6.3.9  Mode Selection (MODE)
      10. 6.3.10 Synchronization (SYNC)
      11. 6.3.11 Power-Down ( PWDN)
      12. 6.3.12 Format[2:0]
      13. 6.3.13 Serial Interface Protocols
      14. 6.3.14 SPI Serial Interface
        1. 6.3.14.1 SCLK
        2. 6.3.14.2 DRDY/FSYNC (SPI Format)
        3. 6.3.14.3 DOUT
        4. 6.3.14.4 DIN
      15. 6.3.15 Frame-Sync Serial Interface
        1. 6.3.15.1 SCLK
        2. 6.3.15.2 DRDY/FSYNC (Frame-Sync Format)
        3. 6.3.15.3 DOUT
        4. 6.3.15.4 DIN
      16. 6.3.16 DOUT Modes
        1. 6.3.16.1 TDM Mode
        2. 6.3.16.2 TDM Mode, Fixed-Position Data
        3. 6.3.16.3 TDM Mode, Dynamic Position Data
        4. 6.3.16.4 Discrete Data Output Mode
      17. 6.3.17 Daisy-Chaining
      18. 6.3.18 Modulator Output
      19. 6.3.19 Pin Test Using Test[1:0] Inputs
      20. 6.3.20 VCOM Output
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.8 Timing Requirements: Frame-Sync Format

over operating free-air temperature range (unless otherwise noted) (4)
SYMBOLPARAMETERMINTYPMAXUNIT
tCLKCLK period (1 / fCLK)All modes3710,000ns
High-Speed mode only30.5ns
tCPWCLK positive or negative pulse width12ns
tCSFalling edge of CLK to falling edge of SCLK–0.250.25tCLK
tFRAMEFrame period (1 / fDATA)(1)2562560tCLK
tFPWFSYNC positive or negative pulse width1tSCLK
tFSRising edge of FSYNC to rising edge of SCLK5ns
tSFRising edge of SCLK to rising edge of FSYNC5ns
tSCLKSCLK period(2)1tCLK
tSPWSCLK positive or negative pulse width0.4tCLK
tDOHD (5) (3)SCLK falling edge to old DOUT invalid (hold time)10ns
tDOPD (3)SCLK falling edge to new DOUT valid (propagation delay)31ns
tMSBPDFSYNC rising edge to DOUT MSB valid (propagation delay)31ns
tDISTNew DIN valid to falling edge of SCLK (setup time)6ns
tDIHD (5)Old DIN valid to falling edge of SCLK (hold time)6ns
(1) Depends on MODE[1:0] and CLKDIV selection. See Table 6-5 (fCLK / fDATA).
(2) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK.
(3) Load on DOUT = 20pF.
(4) Timing parameters are characterized or verified by design for specified temperature but not production tested.
(5) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is > 4ns.
ADS1278QML-SP Frame-Sync Format Timing CharacteristicsFigure 5-2 Frame-Sync Format Timing Characteristics