SLVSKW2 January   2026 ADS1278QML-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Quality Conformance Inspection
    7. 5.7 Timing Requirements: SPI Format
    8. 5.8 Timing Requirements: Frame-Sync Format
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Sampling Aperture Matching
      2. 6.3.2  Frequency Response
        1. 6.3.2.1 High-Speed, Low-Power, And Low-Speed Modes
        2. 6.3.2.2 High-Resolution Mode
      3. 6.3.3  Phase Response
      4. 6.3.4  Settling Time
      5. 6.3.5  Data Format
      6. 6.3.6  Analog Inputs (AINP, AINN)
      7. 6.3.7  Voltage Reference Inputs (VREFP, VREFN)
      8. 6.3.8  Clock Input (CLK)
      9. 6.3.9  Mode Selection (MODE)
      10. 6.3.10 Synchronization (SYNC)
      11. 6.3.11 Power-Down ( PWDN)
      12. 6.3.12 Format[2:0]
      13. 6.3.13 Serial Interface Protocols
      14. 6.3.14 SPI Serial Interface
        1. 6.3.14.1 SCLK
        2. 6.3.14.2 DRDY/FSYNC (SPI Format)
        3. 6.3.14.3 DOUT
        4. 6.3.14.4 DIN
      15. 6.3.15 Frame-Sync Serial Interface
        1. 6.3.15.1 SCLK
        2. 6.3.15.2 DRDY/FSYNC (Frame-Sync Format)
        3. 6.3.15.3 DOUT
        4. 6.3.15.4 DIN
      16. 6.3.16 DOUT Modes
        1. 6.3.16.1 TDM Mode
        2. 6.3.16.2 TDM Mode, Fixed-Position Data
        3. 6.3.16.3 TDM Mode, Dynamic Position Data
        4. 6.3.16.4 Discrete Data Output Mode
      17. 6.3.17 Daisy-Chaining
      18. 6.3.18 Modulator Output
      19. 6.3.19 Pin Test Using Test[1:0] Inputs
      20. 6.3.20 VCOM Output
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.17 Daisy-Chaining

Multiple ADS1278QML-SPs can be daisy-chained together to output data on a single pin. The DOUT1 data output pin of one device is connected to the DIN of the next device. As shown in Figure 6-24, the DOUT1 pin of device 1 provides the output data to a controller, and the DIN of device 2 is grounded. Figure 6-25 shows the data format when reading back data.

The maximum number of channels that can be daisy-chained in this way is limited by the frequency of fSCLK, the mode selection, and the CLKDIV input. The frequency of fSCLK must be high enough to completely shift the data out from all channels within one fDATA period. Table 6-12 lists the maximum number of daisy-chained channels when fSCLK = fCLK.

To increase the number of data channels possible in a chain, a segmented DOUT scheme can be used, producing two data streams. Figure 6-26 illustrates four ADS1278QML-SPs, with pairs of ADS1278QML-SPs daisy-chained together. The channel data of each daisy-chained pair are shifted out in parallel and received by the processor through independent data channels.

Table 6-12 Maximum Channels In A Daisy-Chain (FSCLK = FCLK)
MODE SELECTIONCLKDIVMAXIMUM NUMBER OF CHANNELS
High-Speed110
High-Resolution121
Low-Power121
010
Low-Speed1106
021

Whether the interface protocol is SPI or Frame-Sync, synchronize all devices by tying the SYNC inputs together. When synchronized in SPI protocol, monitor only the DRDY output of one ADS1278QML-SP.

In Frame-Sync interface protocol, the data from all devices are ready after the rising edge of FSYNC.

Since DOUT1 and DIN are both shifted on the falling edge of SCLK, the propagation delay on DOUT1 creates a setup time on DIN. Minimize the skew in SCLK to avoid timing violations.

ADS1278QML-SP Daisy-Chaining of Two Devices, SPI Protocol (Format[2:0] = 000 or 001)
The number of chained devices is limited by the SCLK rate and device mode.
Figure 6-24 Daisy-Chaining of Two Devices, SPI Protocol (Format[2:0] = 000 or 001)
ADS1278QML-SP Daisy-Chain Data Format of Figure 6-24Figure 6-25 Daisy-Chain Data Format of Figure 6-24
ADS1278QML-SP Segmented DOUT Daisy-Chain, Frame-Sync Protocol (Format[2:0] = 011 or 100)
The number of chained devices is limited by the SCLK rate and device mode.
Figure 6-26 Segmented DOUT Daisy-Chain, Frame-Sync Protocol (Format[2:0] = 011 or 100)