SLVUCU5 December 2025 UCD91160 , UCD91320
The System Reset function can generate a programmable system reset signal through a GPIO pin. The System Reset signal is de-asserted when the selected rail voltages reach their respective Power Good On thresholds, and the selected GPIs are asserted, plus a programmable delay time.
The System Reset signal can be asserted immediately when any of the selected rail voltage falls below Power Good Off threshold, or any selected GPI is de-asserted. Alternatively, the System Reset signal can be configured as a pulse once Power Good On is achieved.
The System Reset signal can also integrate the System Watchdog timer. The watchdog is configured with a Start Time and a Reset Time. If these times expire and timeout occurs, it means that the CPU providing the WDI signal is not operating. The System Reset signal is then toggled either using a Delay or GPI Tracking Release Delay to determine if the CPU recovers.
The default state of the System Reset pin is assert. When the System Reset function is configured in-circuit through PMBus commands during normal operation, the pin is briefly asserted by default, even if conditions for de-assert are present. This is because the firmware requires a finite time to examine the de-assert conditions.
See SYSTEM_RESET_CONFIG for more configuration details.