SLVUD83A July   2025  – September 2025 TPS65215-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
    5. 1.5 Caution
  6. 2Hardware
    1. 2.1 Setup
    2. 2.2 TPS65215-Q1 Resources Overview
    3. 2.3 EVM Configuration
      1. 2.3.1 Default EVM Configuration
      2. 2.3.2 Test Points
  7. 3Software
    1. 3.1 Graphical User Interface (GUI)
      1. 3.1.1 Getting Started
        1. 3.1.1.1 Finding the GUI
        2. 3.1.1.2 Downloading the Required Software
        3. 3.1.1.3 Launching the GUI
        4. 3.1.1.4 Connecting to the EVM
      2. 3.1.2 Collateral Page
      3. 3.1.3 Register Map Page
      4. 3.1.4 NVM Configuration Page
        1. 3.1.4.1 NVM Fields
        2. 3.1.4.2 Create and Load a Custom Configuration
      5. 3.1.5 Sequence Configuration
      6. 3.1.6 NVM Programming Page
      7. 3.1.7 Additional Features
  8. 4Hardware Design Files
    1. 4.1 TPS65215Q1EVM Schematic
    2. 4.2 TPS65215Q1EVM PCB Layers
    3. 4.3 TPS65215Q1EVM Bill of Materials
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Revision History

2.3.2 Test Points

The TPS65215Q1EVM EVM contains multiple test points for various measurements. Trace assignments to the test points are shown in the table below.

Table 2-3 TPS65215-Q1 EVM Test Points
Test Point Associated Trace
TP1 VSEL_SD/VSEL_DDR
TP2 GND
TP3 VSYS
TP4-5 GND
TP6 VDD1P8
TP7-10 GND
TP11 MODE/STBY
TP12 GND
TP13 GND
TP14 PB / EN
TP15 Buck 1 Output SENSE
TP16 Buck 2 Output SENSE
TP17 Buck 3 Output SENSE
TP18 LDO 1 Output SENSE
TP20 LDO 2 Output SENSE
TP22 MODE/RST
TP23 Buck 1 Output
TP24 Buck 2 Output
TP25 Buck 3 Output
TP26 LDO 1 Output
TP28 LDO 2 Output
TP30-36 GND
TP37 GPIO

TP38

GPO1
TP39 GPO2
TP40 nINT
TP41 nRSTOUT
TP42 SDA
TP43 USB_5V
TP44 GND
TP45 SCL
TP46 MCU3V3