SLVUD83A July   2025  – September 2025 TPS65215-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
    5. 1.5 Caution
  6. 2Hardware
    1. 2.1 Setup
    2. 2.2 TPS65215-Q1 Resources Overview
    3. 2.3 EVM Configuration
      1. 2.3.1 Default EVM Configuration
      2. 2.3.2 Test Points
  7. 3Software
    1. 3.1 Graphical User Interface (GUI)
      1. 3.1.1 Getting Started
        1. 3.1.1.1 Finding the GUI
        2. 3.1.1.2 Downloading the Required Software
        3. 3.1.1.3 Launching the GUI
        4. 3.1.1.4 Connecting to the EVM
      2. 3.1.2 Collateral Page
      3. 3.1.3 Register Map Page
      4. 3.1.4 NVM Configuration Page
        1. 3.1.4.1 NVM Fields
        2. 3.1.4.2 Create and Load a Custom Configuration
      5. 3.1.5 Sequence Configuration
      6. 3.1.6 NVM Programming Page
      7. 3.1.7 Additional Features
  8. 4Hardware Design Files
    1. 4.1 TPS65215Q1EVM Schematic
    2. 4.2 TPS65215Q1EVM PCB Layers
    3. 4.3 TPS65215Q1EVM Bill of Materials
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Revision History

1.4 Device Information

The TPS65215-Q1 PMIC is a highly integrated power management design for Arm®Cortex®-A53 Processors and FPGAs. This device combines three step down converters and two low-dropout (LDO) regulators. The Buck1 step down converter supports a load current of up to 3.5A, designed for the core rail of a processor. All three step down converters support non-fixed switching frequency or fixed frequency mode. LDO1 is configurable in both load switch and bypass-mode to support SD-Card configuration. All LDO voltage inputs cascade off the system power or the step down converter outputs to enable maximum design and sequencing functionality. Complete with one GPIO, two GPOs, and three Multi-Function-Pins (MFPs), TPS65215-Q1 offers the complete package for full control of the power and sequencing of a System on Chip (SoC).