SLVUD83A July   2025  – September 2025 TPS65215-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
    5. 1.5 Caution
  6. 2Hardware
    1. 2.1 Setup
    2. 2.2 TPS65215-Q1 Resources Overview
    3. 2.3 EVM Configuration
      1. 2.3.1 Default EVM Configuration
      2. 2.3.2 Test Points
  7. 3Software
    1. 3.1 Graphical User Interface (GUI)
      1. 3.1.1 Getting Started
        1. 3.1.1.1 Finding the GUI
        2. 3.1.1.2 Downloading the Required Software
        3. 3.1.1.3 Launching the GUI
        4. 3.1.1.4 Connecting to the EVM
      2. 3.1.2 Collateral Page
      3. 3.1.3 Register Map Page
      4. 3.1.4 NVM Configuration Page
        1. 3.1.4.1 NVM Fields
        2. 3.1.4.2 Create and Load a Custom Configuration
      5. 3.1.5 Sequence Configuration
      6. 3.1.6 NVM Programming Page
      7. 3.1.7 Additional Features
  8. 4Hardware Design Files
    1. 4.1 TPS65215Q1EVM Schematic
    2. 4.2 TPS65215Q1EVM PCB Layers
    3. 4.3 TPS65215Q1EVM Bill of Materials
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Revision History

3.1.4.1 NVM Fields

Register settings are editable on the NVM Configuration Page and follow the register write setting specified on the Register Map page (Immediate or Deferred).

The PMIC Status tab holds a collection of read-only status registers that show the Device ID values as well as all the power rail enables and interrupts, which are displayed as digital LEDs. This section provides fast visual feedback on the PMIC and the operating conditions.

The Power Resources tab holds register settings for each power rail of the PMIC. Here, users also find a reference table for LDO1 and LDO2 configuration settings (for more information on the Load Switch and BYPASS modes, refer to the device data sheet which is included on the Collateral page).

The Sequence tab is used to control power rail sequence and timing registers for both power-up and power-down.

The Digital Pins Configuration tab is used to control settings for digital I/O pins (for details on multi-function pins, see the PMIC data sheet).

The Mask Settings tab allows users to control fault reporting for PMIC protection features, which includes masking for undervoltage, temperature, and interrupt signals.