SLVUDY2 November   2026

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Hardware Overview
    2. 2.2 Jumper Information
      1. 2.2.1 PA10 and PA11 Connection Terminals
      2. 2.2.2 Bottom Sigma Delta Header Block
    3. 2.3 Power Requirements
    4. 2.4 XDS110 Debug Probe
      1. 2.4.1 Isolation Jumper Block
    5. 2.5 Measure Current Draw of the MSPM0G3708
    6. 2.6 Clocking
    7. 2.7 BoosterPack Plug-in Module Pinout
    8. 2.8 Sigma Delta ADC Inputs
  9. 3Software
    1. 3.1 Software Development Options
    2. 3.2 TI Energy Metrology Studio
    3. 3.3 Software Development: CCS
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Compliance and Certifications
    2. 5.2 Trademarks

2.6 Clocking

The internal SYSOSC is 32MHz by default with an accuracy of 2.5%. The MCLK is sourced by the SYSOSC by default. The SYSPLL can be used to generate a clock signal up to 80MHz, which can be used to source MCLK. CPUCLK is sourced directly from MCLK in RUN mode and disabled in other modes. The low-power clock (ULPCLK) can be sourced by MCLK and active in RUN and SLEEP mode by configuration. The part also includes an internal 32kHz oscillator, LFOSC, which is the default low frequency source. Two clock crystal options are included on the LaunchPad, one option is a high-frequency 40MHz crystal (HFXT), and the other option is a low-frequency 32.768kHz crystal (LFXT). Select the crystals during application programming as the clock source for the high frequency and low frequency clocks. For more clock tree details, see the Clock Module (CKM) section of the MSPM0 G-Series 80MHz Microcontrollers technical reference manual.