Beyond switching noise, continuous self-noise, with thermal and flicker noise components in the range of 0.1Hz to 100kHz, are of concern at lower I_Q biasing. Because the reference is usually the largest noise contributor, choosing integrated versions of sample-and-hold techniques to create both voltage and current references offer a compelling trade-off between area, noise, I_Q and robust performance (no drift) over the life of the device. The drawback of such sample-and-hold circuits are the small ripple errors created.

Figure 13 illustrates a design using TI’s precision digital-to-analog converter (DAC) and operational amplifier families that attempts to optimize sample-and-hold operation so that any glitch created is well within the noise floor of the regulator in question. Some of these techniques are employed to remove the glitch and unwanted tones in TPS7A02 LDO design.

As shown in Figure 14, the TPS7A02 device’s sample-and-hold noise-shaping reduces integrated noise >40% in the 10 to 100Hz frequency band.