The goals of a nanopower process can conflict with the goals of high-performance deep-submicron technologies, which prioritize speed and gate density over I_Q reduction. While process technologies may vary, the vast majority of leakages come from large digital circuits, memory and high-power FETs. The accuracy of always-on circuitry tends to be limited to the ability to control components such resistors and capacitors and a mismatch between transistors. Not having the right components to address the leakage and control of always-on circuits manifests itself in large typical and worst-case I_Q and I_SHDN ratios across temperature. A dedicated low-power process technology with the right components can provide a clear manufacturing advantage.

One fundamental challenge is to reliably operate components biased in the subthreshold region. One common problem seen is increased random threshold voltage (V_T) mismatch. Figure 9 shows a mechanism reported in literature that increases random mismatch by a thinning of oxide in the shallow trench isolation (STI) at the edge of the transistor. This parallel low-V_T edge transistor seen in Figure 9, distorts the V_T of the intentional transistor, resulting in much higher random mismatch for the most basic analog circuits like differential pairs and current mirrors. These mismatches can degrade the output voltage or mode control accuracy over temperature which can be clearly observed in the data sheet.