SLYY245 March   2025 DRV7308

 

  1.   1
  2.   Overview
  3.   At a glance
  4.   Introduction
  5.   How package variations meet market demands
  6.   Cost efficiency
  7.   Power efficiency
  8.   Enabling miniature products
  9.   Precision solutions
  10.   High voltage
  11.   Isolation
  12.   Multiple chips in one package
  13.   Reliability testing for packaging
  14.   Space-grade packages
  15.   Conclusion
  16.   Additional resources

Multiple chips in one package

Some designs benefit from the ability to integrate multiple silicon nodes into a single package. For example, battery-management chips such as the BQ40Z50-R2 (see Figure 19) combine low-cost logic with flash memory and high-precision voltage measurement by stacking silicon.

TI’s BQ40Z50-R2 battery-management IC features two silicon technologies in a single package. Figure 19 TI’s BQ40Z50-R2 battery-management IC features two silicon technologies in a single package.

Multichip packaging can also increase silicon density in a device. Figure 20 demonstrates how the silicon area exceeds the physical footprint of the package by stacking multiple chips, doubling the available channels in an analog front-end device.

A multichip analog front-end package with increased density through silicon stacking. Figure 20 A multichip analog front-end package with increased density through silicon stacking.

Figure 21 shows a top view of an analog front-end package with two wires connecting each chip to each lead.

Top view of an analog front-end package. Figure 21 Top view of an analog front-end package.