SLYY245 March   2025 DRV7308

 

  1.   1
  2.   Overview
  3.   At a glance
  4.   Introduction
  5.   How package variations meet market demands
  6.   Cost efficiency
  7.   Power efficiency
  8.   Enabling miniature products
  9.   Precision solutions
  10.   High voltage
  11.   Isolation
  12.   Multiple chips in one package
  13.   Reliability testing for packaging
  14.   Space-grade packages
  15.   Conclusion
  16.   Additional resources

Cost efficiency

When optimizing the PCB, package and silicon for cost, minimizing the size of the silicon will lower costs; however, many applications may require larger packages with a large input/output (I/O) pitch. In Figure 4, spacing of the I/O pads are <100µm on the silicon to enable a small chip size, while these same I/Os are fanned out to >650µm to meet the design constraints for a low-cost PCB.

I/O spacing <100µm is typical for a compact chip design, while I/O spacing >650µm fits with low-cost PCB designs. Figure 4 I/O spacing <100µm is typical for a compact chip design, while I/O spacing >650µm fits with low-cost PCB designs.

Standardizing PCB dimensions and package sizes for commodity, general-purpose products makes it possible to purchase identical parts from multiple suppliers. Additionally, such packages offer the flexibility for the silicon to continue shrinking (which again, lowers costs) without impacting the fit in an end application. In some cases, packages can be shrunk while still allowing for industry-standard footprints. This enables a migration toward miniature packages with backward compatibility for existing PCB layouts.