SLYY245 March   2025 DRV7308

 

  1.   1
  2.   Overview
  3.   At a glance
  4.   Introduction
  5.   How package variations meet market demands
  6.   Cost efficiency
  7.   Power efficiency
  8.   Enabling miniature products
  9.   Precision solutions
  10.   High voltage
  11.   Isolation
  12.   Multiple chips in one package
  13.   Reliability testing for packaging
  14.   Space-grade packages
  15.   Conclusion
  16.   Additional resources

High voltage

Creating devices that operate at voltages exceeding 650V presents particular challenges. Preventing arcing outside the package requires adherence to strict industry standards for lead spacing and package design. Internally, materials such as specialized mold compounds must prevent dielectric breakdown over long periods of high temperatures, high humidity and a large bias voltage. Precise electric field analysis of package structures helps prevent arcing inside the package.

Figure 17 shows the LMG3624 650V, 170mΩ GaN FET in a QFN package, which uses special high-voltage plastic and lead spacing. Additionally, the LMG3650R035 650V, 35mΩ GaN FET with integrated driver and protection supports currents up to 36A with greater thermal dissipation from a transistor outline leadless (TOLL) package with a thermal pad.

The 650V, 170mΩ GaN FET uses a QFN package for miniaturization while maintaining lead spacing to support high voltages. The 650V, 35mΩ GaN FET in TI’s TOLL package with a thermal pad supports higher currents with improved thermal management. Figure 17 The 650V, 170mΩ GaN FET uses a QFN package for miniaturization while maintaining lead spacing to support high voltages. The 650V, 35mΩ GaN FET in TI’s TOLL package with a thermal pad supports higher currents with improved thermal management.