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Clocks & timing

Simplify your clock tree design with our clock buffers

Devices with low additive jitter and skew that minimize system complexity

Our broad portfolio of clock buffers features low additive jitter performance, low output skew and a wide operating temperature range for industry-standard output formats including LVCMOS, LVDS, LVPECL and HCSL. These buffers are optimized for use in a wide range of performance-oriented and cost-sensitive applications.

Single-ended buffers

Optimize your design and generate multiple copies of your LVCMOS clock source with our easy-to-use single-ended buffers. These buffers support frequencies up to 350 MHz, and feature additive jitter of 100-fs RMS and a power supply from 1.5 to 3.3 V.

Differential buffers

Generate multiple output frequencies for LVDS, LVPECL, HCSL and CML with our differential buffers. These buffers support frequencies up to 3.2 GHz, and feature additive jitter of 100-fs RMS (typical) and a power supply from 2.5 to 3.3 V.

Configurable buffers

Generate multiple output frequencies for a range of protocols with our configurable (pin-programmable) clock buffers. These buffers feature universal support for input and output formats, and additive jitter of less than 30-fs RMS.

Specialty buffers

Optimize system design in industrial and memory applications with our portfolio of specialty buffers with lower additive jitter, including zero-delay buffers, DDR memory buffers, and divider buffers.

Featured clock buffers


Fanout buffer with 4 LVCMOS outputs, support for 1.8/2.5/3.3-V supply voltage, additive jitter less than 50 fs (RMS) and backward compatibility to CDCLVC1104


Fanout buffer with four LVDS outputs, additive jitter of less than 300 fs and support for clock frequencies up to 800 MHz


Pin-programmable buffer with 10 outputs, ultra-low additive jitter of less than 30 fs, and support for output frequencies up to 3 GHz


Functions as a zero-delay buffer because of an integrated PLL with a feedback loop for delay compensation and signal reconditioning

Featured technical documentation

How to Apply 1.8-V Signals to 3.3-V CDCLVC11xx Fanout Clock Buffer

Learn how the CDCLVC11xx family of low-jitter LVCMOS fanout buffers supports input signals with a voltage level up to 1.8 V by implementing an external RC network.

AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)

Refer to this application report for AC-coupling techniques used to interface between different logic levels, specifically LVPECL, LVDS, HSTL and CML.

Clocking Design Guidelines: Unused Pins

Use these guidelines as a supplement to the device data sheet for detailed information about unused device pins.

Technical Article

Featured clock buffer technical articles