Clock buffers

Simplify your clock tree design with our clock buffers

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Our broad portfolio of clock buffers features low additive jitter performance, low output skew and a wide operating temperature range for industry-standard output formats including LVCMOS, LVDS, LVPECL and HCSL. These buffers are optimized for use in a wide range of performance-oriented and cost-sensitive applications.

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Single-ended buffers

Optimize your design and generate multiple copies of your LVCMOS clock source with our easy-to-use single-ended buffers.

Differential buffers

Generate multiple output frequencies for LVDS, LVPECL, HCSL and CML with our differential buffers.

Configurable buffers

Generate multiple output frequencies for a range of protocols with our configurable (pin-programmable) clock buffers.

Specialty buffers

Optimize system design in industrial and memory applications with our portfolio of specialty buffers with lower additive jitter, including zero-delay buffers, DDR memory buffers, and divider buffers.

Featured clock buffers

LMK1D1208I NEW

8-channel output, 1.8-V, 2.5-V, and 3.3-V LVDS buffer with I²C

Approx. price (USD) 1ku | 6.387
LMK1D1208P NEW

8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer with pin control

Approx. price (USD) 1ku | 6.387
CDCDB400 NEW

4-output clock buffer for PCIe® Gen 1 to Gen 5

Approx. price (USD) 1ku | 1.365
LMK1D2106 NEW

Dual bank 6-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer

Approx. price (USD) 1ku | 6.335
LMK1D1216 NEW

16-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer

Approx. price (USD) 1ku | 7.015
LMK1D2108 NEW

Dual bank 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer

Approx. price (USD) 1ku | 7.384

Technical resources

Application note
Application note
How to Apply 1.8-V Signals to 3.3-V CDCLVC11xx Fanout Clock Buffer
Learn how the CDCLVC11xx family of low-jitter LVCMOS fanout buffers supports input signals with a voltage level up to 1.8 V by implementing an external RC network.
document-pdfAcrobat PDF
Application note
Application note
AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
Refer to this application report for AC-coupling techniques used to interface between different logic levels, specifically LVPECL, LVDS, HSTL and CML.
document-pdfAcrobat PDF
Application note
Application note
Clocking Design Guidelines: Unused Pins
Use these guidelines as a supplement to the device data sheet for detailed information about unused device pins. 
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