Simplify your clock tree design with our clock buffers
Devices with low additive jitter and skew that minimize system complexity
Our broad portfolio of clock buffers features low additive jitter performance, low output skew and a wide operating temperature range for industry-standard output formats including LVCMOS, LVDS, LVPECL and HCSL. These buffers are optimized for use in a wide range of performance-oriented and cost-sensitive applications.
Optimize your design and generate multiple copies of your LVCMOS clock source with our easy-to-use single-ended buffers. These buffers support frequencies up to 350 MHz, and feature additive jitter of 100-fs RMS and a power supply from 1.5 to 3.3 V.
Generate multiple output frequencies for LVDS, LVPECL, HCSL and CML with our differential buffers. These buffers support frequencies up to 3.2 GHz, and feature additive jitter of 100-fs RMS (typical) and a power supply from 2.5 to 3.3 V.
Generate multiple output frequencies for a range of protocols with our configurable (pin-programmable) clock buffers. These buffers feature universal support for input and output formats, and additive jitter of less than 30-fs RMS.
Optimize system design in industrial and memory applications with our portfolio of specialty buffers with lower additive jitter, including zero-delay buffers, DDR memory buffers, and divider buffers.
Featured clock buffers
Featured technical documentation
Learn how the CDCLVC11xx family of low-jitter LVCMOS fanout buffers supports input signals with a voltage level up to 1.8 V by implementing an external RC network.
Refer to this application report for AC-coupling techniques used to interface between different logic levels, specifically LVPECL, LVDS, HSTL and CML.