Simplify your clock tree design with our clock buffers
Our broad portfolio of clock buffers features low additive jitter performance, low output skew and a wide operating temperature range for industry-standard output formats including LVCMOS, LVDS, LVPECL and HCSL. These buffers are optimized for use in a wide range of performance-oriented and cost-sensitive applications.
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Optimize your design and generate multiple copies of your LVCMOS clock source with our easy-to-use single-ended buffers.
Generate multiple output frequencies for LVDS, LVPECL, HCSL and CML with our differential buffers.
Generate multiple output frequencies for a range of protocols with our configurable (pin-programmable) clock buffers.
Optimize system design in industrial and memory applications with our portfolio of specialty buffers with lower additive jitter, including zero-delay buffers, DDR memory buffers, and divider buffers.
Featured clock buffers
1.2-V to 1.8-V clock buffer and level translator
Approx. price (USD) 1ku | 0.5
How to Apply 1.8-V Signals to 3.3-V CDCLVC11xx Fanout Clock Buffer
Learn how the CDCLVC11xx family of low-jitter LVCMOS fanout buffers supports input signals with a voltage level up to 1.8 V by implementing an external RC network.
AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
Refer to this application report for AC-coupling techniques used to interface between different logic levels, specifically LVPECL, LVDS, HSTL and CML.
Clocking Design Guidelines: Unused Pins
Use these guidelines as a supplement to the device data sheet for detailed information about unused device pins.