SNAS764 May 2018 LMX2572LP
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CAL_CLK_DIV | ||
R/W-101h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 - 3 | R/W | 101h | Program 101h to this field. | |
2 - 0 | CAL_CLK_DIV | R/W | 0h | Divides down the state machine clock during VCO calibration. Maximum state machine clock frequency is 200 MHz.
State machine clock frequency = fOSCin / (2CAL_CLK_DIV). 0: fOSCin ≤ 200 MHz 1: 200 MHz < fOSCin ≤ 250 MHz All other values are not used. |