Product details

Frequency (max) (MHz) 2000 Frequency (min) (MHz) 12.5 Normalized PLL phase noise (dBc/Hz) -232 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -123.5 Features FSK modulation, Flexible ramp generation, Integer-boundary spurs (IBS) removal, Integrated VCO, Phase adjustment, Wideband Current consumption (mA) 70 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 2000 Frequency (min) (MHz) 12.5 Normalized PLL phase noise (dBc/Hz) -232 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -123.5 Features FSK modulation, Flexible ramp generation, Integer-boundary spurs (IBS) removal, Integrated VCO, Phase adjustment, Wideband Current consumption (mA) 70 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
VQFN (RHA) 40 36 mm² 6 x 6
  • Output Frequency: 12.5 MHz to 2 GHz
  • Low Power Consumption: 70 mA at 3.3-V Supply
  • –124-dBc/Hz Phase Noise at 100-kHz Offset With 800-MHz Carrier
  • PLL Figure of Merit: –232 dBc/Hz
  • PLL Normalized 1/f Noise: –123.5 dBc/Hz
  • 32-Bit Fractional-N Divider
  • Remove Integer Boundary Spurs With Programmable Input Multiplier
  • Synchronization of Output Phase Across Multiple Devices
  • Support for Ramp and Chirp Functions
  • Support for FSK Direct Digital Modulation
  • Two Programmable Output Power Level Differential Outputs
  • Fast VCO Calibration Speed: < 20 µs
  • Single 3-V to 3.5-V Power Supply
  • Output Frequency: 12.5 MHz to 2 GHz
  • Low Power Consumption: 70 mA at 3.3-V Supply
  • –124-dBc/Hz Phase Noise at 100-kHz Offset With 800-MHz Carrier
  • PLL Figure of Merit: –232 dBc/Hz
  • PLL Normalized 1/f Noise: –123.5 dBc/Hz
  • 32-Bit Fractional-N Divider
  • Remove Integer Boundary Spurs With Programmable Input Multiplier
  • Synchronization of Output Phase Across Multiple Devices
  • Support for Ramp and Chirp Functions
  • Support for FSK Direct Digital Modulation
  • Two Programmable Output Power Level Differential Outputs
  • Fast VCO Calibration Speed: < 20 µs
  • Single 3-V to 3.5-V Power Supply

The LMX2572LP is a low-power, high-performance wideband synthesizer that can generate one frequency from 12.5 MHz to 2 GHz without the use of an internal doubler. The PLL delivers excellent performance while consuming just 70 mA from a single 3.3-V supply.

For applications like digital mobile radio (DMR) and wireless microphones, the LMX2572LP supports FSK modulation. Discrete level FSK and pulse-shaping FSK are supported. Direct digital FSK modulation is achievable through programming or pins.

The LMX2572LP allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. The LMX2572LP provides an option to adjust the phase with fine granularity to account for delay mismatch on the board or within devices. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows the user to change frequencies faster than 20 µs.

The LMX2572LP integrates LDOs from a single 3.3-V supply, thus eliminating the need for onboard low-noise LDOs.

The LMX2572LP is a low-power, high-performance wideband synthesizer that can generate one frequency from 12.5 MHz to 2 GHz without the use of an internal doubler. The PLL delivers excellent performance while consuming just 70 mA from a single 3.3-V supply.

For applications like digital mobile radio (DMR) and wireless microphones, the LMX2572LP supports FSK modulation. Discrete level FSK and pulse-shaping FSK are supported. Direct digital FSK modulation is achievable through programming or pins.

The LMX2572LP allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. The LMX2572LP provides an option to adjust the phase with fine granularity to account for delay mismatch on the board or within devices. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows the user to change frequencies faster than 20 µs.

The LMX2572LP integrates LDOs from a single 3.3-V supply, thus eliminating the need for onboard low-noise LDOs.

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* Data sheet LMX2572LP 2-GHz Low Power Wideband RF Synthesizer With FSK Modulation datasheet PDF | HTML 24 May 2018
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 11 Apr 2025
Application brief Compilation of RF Synthesizer Resources PDF | HTML 22 Oct 2024
Application note LMX2571 Using a Programmable Input Multiplier to Minimize Integer Boundary Spurs 12 Jan 2016

Design & development

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Evaluation board

LMX2572LPEVM — 2-GHz Low Power Wideband RF Synthesizer with FSK Modulation Evaluation Module

This Evaluation Module (EVM) is for the LMX2572LP, which is a low-power high-performance wideband synthesizer that can generate any frequency from 12.5 MHz to 2 GHz without using an internal doubler. The PLL delivers excellent performance while consuming just 70 mA from a single 3.3-V supply. By (...)
User guide: PDF
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Evaluation board

XMICR-3P-LMX2572 — LMX2572 X-MWblock evaluation modules

X-MWblocks consist of RF and Microwave “Drop-In” components that can be used individually for prototyping or in production assemblies. X-MWblocks are easy to test, integrate, align, and configure to 60 GHz and beyond. No messy Sweat Soldering or Silver Epoxy processes are required. (...)

From: X-Microwave
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TICSPRO-SW TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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PLLATINUMSIM-SW PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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VQFN (RHA) 40 Ultra Librarian

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