SNAS786C July   2020  – July 2025 CDCE6214-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  EEPROM Characteristics
    6. 5.6  Reference Input, Single-Ended Characteristics
    7. 5.7  Reference Input, Differential Characteristics
    8. 5.8  Reference Input, Crystal Mode Characteristics
    9. 5.9  General-Purpose Input Characteristics
    10. 5.10 Triple Level Input Characteristics
    11. 5.11 Logic Output Characteristics
    12. 5.12 Phase Locked Loop Characteristics
    13. 5.13 Closed-Loop Output Jitter Characteristics
    14. 5.14 Input and Output Isolation
    15. 5.15 Buffer Mode Characteristics
    16. 5.16 PCIe Spread Spectrum Generator
    17. 5.17 LVCMOS Output Characteristics
    18. 5.18 LP-HCSL Output Characteristics
    19. 5.19 LVDS Output Characteristics
    20. 5.20 Output Synchronization Characteristics
    21. 5.21 Power-On Reset Characteristics
    22. 5.22 I2C-Compatible Serial Interface Characteristics
    23. 5.23 Timing Requirements, I2C-Compatible Serial Interface
    24. 5.24 Power Supply Characteristics
    25. 5.25 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Reference Inputs
    2. 6.2 Outputs
    3. 6.3 Serial Interface
    4. 6.4 PSNR Test
    5. 6.5 Clock Interfacing and Termination
      1. 6.5.1 Reference Input
      2. 6.5.2 Outputs
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference Block
        1. 7.3.1.1 Zero Delay Mode, Internal and External Path
      2. 7.3.2 Phase-Locked Loop (PLL)
        1. 7.3.2.1 PLL Configuration and Divider Settings
        2. 7.3.2.2 Spread Spectrum Clocking
        3. 7.3.2.3 Digitally-Controlled Oscillator and Frequency Increment or Decrement - Serial Interface Mode and GPIO Mode
      3. 7.3.3 Clock Distribution
        1. 7.3.3.1 Glitchless Operation
        2. 7.3.3.2 Divider Synchronization
        3. 7.3.3.3 Global and Individual Output Enable
      4. 7.3.4 Power Supplies and Power Management
      5. 7.3.5 Control Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Modes
        1. 7.4.1.1 Fall-Back Mode
        2. 7.4.1.2 Pin Mode
        3. 7.4.1.3 Serial Interface Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 EEPROM
        1. 7.5.2.1 EEPROM - Cyclic Redundancy Check
        2. 7.5.2.2 Recommended Programming Procedure
        3. 7.5.2.3 EEPROM Access
          1. 7.5.2.3.1 Register Commit Flow
          2. 7.5.2.3.2 Direct Access Flow
        4. 7.5.2.4 Register Bits to EEPROM Mapping
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Up Sequence
      2. 8.3.2 Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

7.3.1.1 Zero Delay Mode, Internal and External Path

The CDCE6214-Q1 can operate in Zero Delay Mode with internal as well as external feedback. In Zero Delay Mode, PRIREF clock is used as the reference clock to the PFD. SECREF input clock can be used to feed an external source as feedback clock to the PFD. External feedback path is recommended for Zero Delay operation. Moreover there is an additional internal feedback path which is sourced from output channel 2. The Input-output propagation delay is expected to be higher in internal Zero Delay Mode than in external Zero Delay Mode.

Table 7-2 Zero Delay Operation
OPERATION(1)(2) REFSEL R2[1:0] - REFSEL_SW R24[1:0] - IP_SECREF_BUF_SEL(3) R24[15] - IP_PRIREF_BUF_SEL(3) R0[8] - ZDM_EN R0[10] - ZDM_CLOCKSEL DESCRIPTION
Normal Operation, XTAL Input L 0h or 1h or 2h 0h X 0h 0h Normal Operation, XTAL Input
Normal Operation, Differential Input L 0h or 1h or 2h 2h or 3h X 0h 0h SECREF/Differential Input
Normal Operation, Differential Input H 0h or 1h or 3h X 1h 0h 0h PRIREF/Differential Input
Normal Operation, LVCMOS Input L 0h or 1h or 2h 1h X 0h 0h SECREF/LVCMOS Input
Normal Operation, LVCMOS Input H 0h or 1h or 3h X 0h 0h 0h PRIREF/LVCMOS Input
External Zero Delay Mode, Differential Input H 0h or 1h or 3h 2h or 3h 1h 1h 1h Input Clock on PRIREF, Feedback clock on SECREF
External Zero Delay Mode, LVCMOS Input H 0h or 1h or 3h 1h 0h 1h 1h Input Clock on PRIREF, Feedback clock on SECREF
Internal Zero Delay Mode, Differential Input H 0h or 1h or 3h X 1h 1h 0h Input clock on PRIREF
Internal Zero Delay Mode, Differential Input H 0h or 1h or 3h X 0h 1h 0h Input clock in PRIREF
(1) In Zero Delay Mode, all dividers must be programmed such that PLL can lock. On power-up in Zero Delay Mode, PLL locks automatically
(2) For internal Zero Delay Mode, channel 2 is required. Channel 2 must not be powered down
(3) "X" allows any possible bit field value without any impact on the functionality
CDCE6214-Q1 Input/Output Alignment in External Zero Delay Mode for LVCMOS Output Figure 7-2 Input/Output Alignment in External Zero Delay Mode for LVCMOS Output