SNVSC77B December   2024  – April 2025 LM5125-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)
      2. 6.3.2  Device and Phase Enable/Disable (UVLO/EN, EN2)
      3. 6.3.3  Switching Frequency and Synchronization (SYNCIN)
      4. 6.3.4  Dual Random Spread Spectrum (DRSS)
      5. 6.3.5  Operation Modes (BYPASS, DEM, FPWM)
      6. 6.3.6  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      7. 6.3.7  Soft Start (SS-pin)
      8. 6.3.8  VOUT Programming (VOUT, ATRK, DTRK)
      9. 6.3.9  Protections
        1. 6.3.9.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.9.2 Thermal Shutdown (TSD)
      10. 6.3.10 Power-Good Indicator (PGOOD-pin)
      11. 6.3.11 Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      12. 6.3.12 Current Sense Setting and Switch Peak Current Limit (CSP1, CSP2, CSN1, CSN2)
      13. 6.3.13 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      14. 6.3.14 Maximum Duty Cycle and Minimum Controllable On-time Limits
      15. 6.3.15 Signal Deglitch Overview
      16. 6.3.16 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
      2. 7.1.2 Non-synchronous Application
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Determine the Total Phase Number
        2. 7.2.3.2  Determining the Duty Cycle
        3. 7.2.3.3  Timing Resistor RT
        4. 7.2.3.4  Inductor Selection Lm
        5. 7.2.3.5  Current Sense Resistor Rcs
        6. 7.2.3.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.3.7  Low-Side Power Switch QL
        8. 7.2.3.8  High-Side Power Switch QH
        9. 7.2.3.9  Snubber Components
        10. 7.2.3.10 Vout Programming
        11. 7.2.3.11 Input Current Limit (ILIM/IMON)
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 CFG Settings
        15. 7.2.3.15 Output Capacitor Cout
        16. 7.2.3.16 Input Capacitor Cin
        17. 7.2.3.17 Bootstrap Capacitor
        18. 7.2.3.18 VCC Capacitor CVCC
        19. 7.2.3.19 BIAS Capacitor
        20. 7.2.3.20 VOUT Capacitor
        21. 7.2.3.21 Loop Compensation
      4. 7.2.4 Performance Data and Results
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 AC Loop Response Curve
        5. 7.2.4.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.3.17 Bootstrap Capacitor

The bootstrap capacitor between the HBx and SWx pin supplies the gate current to charge the high-side MOSFET device gate during each turn-on cycle and also supplies recovery charge for the bootstrap diode. These current peaks are several amperes. The recommended value of the bootstrap capacitor is 0.1μF. Use good-quality, low-ESR, ceramic capacitor for CBST. Place CBST close to the pins of the device to minimize potentially damaging voltage transients caused by trace inductance. The minimum value for the bootstrap capacitor is calculated as follows,

Equation 72. CBST=QGΔVBST

where

  • QG is the high-side MOSFET gate charge at VCC = 5V
  • ΔVBST is the tolerable voltage droop on CBST, which is typically less than 5% of VCC or 0.15V, conservatively

In this example, the value of the bootstrap capacitors (CBST) are 0.1µF.