SNVSC77B December   2024  – April 2025 LM5125-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)
      2. 6.3.2  Device and Phase Enable/Disable (UVLO/EN, EN2)
      3. 6.3.3  Switching Frequency and Synchronization (SYNCIN)
      4. 6.3.4  Dual Random Spread Spectrum (DRSS)
      5. 6.3.5  Operation Modes (BYPASS, DEM, FPWM)
      6. 6.3.6  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      7. 6.3.7  Soft Start (SS-pin)
      8. 6.3.8  VOUT Programming (VOUT, ATRK, DTRK)
      9. 6.3.9  Protections
        1. 6.3.9.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.9.2 Thermal Shutdown (TSD)
      10. 6.3.10 Power-Good Indicator (PGOOD-pin)
      11. 6.3.11 Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      12. 6.3.12 Current Sense Setting and Switch Peak Current Limit (CSP1, CSP2, CSN1, CSN2)
      13. 6.3.13 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      14. 6.3.14 Maximum Duty Cycle and Minimum Controllable On-time Limits
      15. 6.3.15 Signal Deglitch Overview
      16. 6.3.16 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
      2. 7.1.2 Non-synchronous Application
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Determine the Total Phase Number
        2. 7.2.3.2  Determining the Duty Cycle
        3. 7.2.3.3  Timing Resistor RT
        4. 7.2.3.4  Inductor Selection Lm
        5. 7.2.3.5  Current Sense Resistor Rcs
        6. 7.2.3.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.3.7  Low-Side Power Switch QL
        8. 7.2.3.8  High-Side Power Switch QH
        9. 7.2.3.9  Snubber Components
        10. 7.2.3.10 Vout Programming
        11. 7.2.3.11 Input Current Limit (ILIM/IMON)
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 CFG Settings
        15. 7.2.3.15 Output Capacitor Cout
        16. 7.2.3.16 Input Capacitor Cin
        17. 7.2.3.17 Bootstrap Capacitor
        18. 7.2.3.18 VCC Capacitor CVCC
        19. 7.2.3.19 BIAS Capacitor
        20. 7.2.3.20 VOUT Capacitor
        21. 7.2.3.21 Loop Compensation
      4. 7.2.4 Performance Data and Results
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 AC Loop Response Curve
        5. 7.2.4.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 150°C. Unless otherwise stated, VI = VBIAS = 12V, VOUT = 24V, RT = 14kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT (BIAS, VCC, VOUT)
ISD VI current in shutdown state (BIAS connected to VI). Current into BIAS, CSP1, CSN1, CSP2, CSN2, SW1, SW2. VEN/UVLO = 0 V, VOUT = 12V, TJ = –40°C to 125°C 2 5 µA
ISD_BIAS BIAS-pin current in shutdown state VEN/UVLO = 0V, VOUT = 12V, TJ = –40°C to 125°C 2 5 µA
ISD_VOUT VOUT-pin current in shutdown state VEN/UVLO = 0V, VOUT = 12V, TJ = –40°C to 125°C 0.001 0.5 µA
IQ_BIAS_FPWM BIAS-pin quiescent current in active state, FPWM-Mode, internal clock (not-switching, RT and IMON current is excluded) 1-phase, VEN/UVLO = 2.0V, VEN2 = 0V, VCFG2 = 0V, VATRK = 0.667V, TJ = –40°C to 125°C 1.1 1.5 mA
2-phase, VEN/UVLO = 2.0V, VEN2 = 2V, VCFG2 = 0V, VATRK = 0.667V, TJ = –40°C to 125°C 1.6 2 mA
IQ_BIAS_DEM BIAS-pin quiescent current  in active state, DEM-Mode, internal clock (not-switching, RT and IMON current is excluded) 1-phase, VEN/UVLO = 2.0V, VEN2 = 0V, VCFG2 = 0V, VATRK = 0.667V, TJ = –40°C to 125°C 1.1 1.5 mA
2-phase, VEN/UVLO = 2.0V, VEN2 = 2V, VCFG2 = 0V, VATRK = 0.667V, TJ = –40°C to 125°C 1.6 2 mA
IQ_VOUT_FPWM VOUT-pin quiescent current in active state, FPWM-Mode, internal clock (not-switching) 2-phase, VEN/UVLO = 2.0V, VEN2 = 2V, VCFG2 = 0V, VATRK = 0.667V, TJ = –40°C to 125°C 250 300 µA
IQ_BIAS_BYP BIAS-pin current in bypass state (RT and IMON current is excluded) 1-phase, VEN/UVLO = 2.0V, VEN2 = 0V, VCFG2 = 0V, VOUT = 12V, TJ = –40°C to 125°C 1 1.5 mA
BIAS-pin current in bypass state (RT and IMON current is excluded) 2-phase, VEN/UVLO = 2.0V, VEN2 = 2V, VCFG2 = 0V, VOUT = 12V, TJ = –40°C to 125°C 1.5 2.0 mA
IQ_VOUT_BYP VOUT-pin current in bypass state 2-phase, VEN/UVLO = 2.0V, VEN2 = 2V, VCFG2 = 0V, VOUT = 12V, TJ = –40°C to 125°C, no resistor between HO and SW. 280 330 µA
IBIAS BIAS-pin bias current VBIAS = 12V, IVCC = 200mA 200 210 mA
IVOUT VOUT-pin bias current when VCC is supplied by VOUT VBIAS = 3.3V, IVCC = 200mA 200 230 mA
VCC REGULLATOR (VCC)
VBIAS-RISING Threshold to switch VCC supply from VOUT-pin to BIAS-pin VBIAS rising 4.25 4.35 4.45 V
VBIAS-FALLING Threshold to switch VCC supply from BIAS-pin to VOUT-pin VBIAS falling 4.1 4.2 4.3 V
VBIAS-HYS VCC supply threshold hysteresis 100 150 mV
VVCC-REG1 VCC regulation No load 4.75 5 5.25 V
VVCC-REG2 VCC regulation during dropout VBIAS = 4.5V, IVCC = 110mA 4 4.3 V
VVCC-UVLO-RISING VCC UVLO threshold VCC rising 3.4 3.5 3.6 V
VVCC-UVLO-FALLING VCC UVLO threshold VCC falling 3.2 3.3 3.4 V
VVCC-UVLO-HYS VCC UVLO threshold hysteresis VCC falling 215 mV
IVCC-CL VCC sourcing current limit VVCC = 4V 200 mA
ENABLE (EN/UVLO)
VEN-RISING Enable threshold EN rising 0.50 0.55 0.6 V
VEN-FALLING Enable threshold EN falling 0.40 0.45 0.50 V
VEN-HYS Enable hysteresis EN falling 100 mV
REN EN pulldown resistance VEN = 0.2V 30 37 50 kΩ
VUVLO-RISING UVLO threshold UVLO rising 1.05 1.1 1.15 V
VUVLO-FALLING UVLO threshold UVLO falling 1.025 1.075 1.125 V
VUVLO-HYS UVLO hysteresis UVLO falling 25 mV
IUVLO-HYS UVLO pulldown hysteresis current VUVLO  = 0.7V 9 10 11 µA
IUVLO/EN UVLO/EN-pin bias current VUVLO/EN = 0.3V, pull-down resistor = active. 8 11 µA
VUVLO/EN = 0.7V, 10µA current = active. 9 10 11 µA
VUVLO/EN = 3.3V 1 µA
CH2 ENABLE (EN2)
VEN2_H Enable 2 high level input voltage EN2 rising 1.19 5.25 V
VEN2_L Enable 2 low level input voltage EN2 falling –0.3 0.41 V
IEN2 Enable 2 bias current EN1 = EN2 = 3.3V 0.01 1 µA
CONFIGURATION (CFG0, CFG1, CFG2)
RCFGx_1 Level 1 resistance 0 0.1 kΩ
RCFGx_2 Level 2 resistance 0.496 0.51 0.526 kΩ
RCFGx_3 Level 3 resistance 1.11 1.15 1.19 kΩ
RCFGx_4 Level 4 resistance 1.81 1.9 1.93 kΩ
RCFGx_5 Level 5 resistance 2.65 2.7 2.82 kΩ
RCFGx_6 Level 6 resistance 3.71 3.8 3.94 kΩ
RCFGx_7 Level 7 resistance 4.95 5.1 5.26 kΩ
RCFGx_8 Level 8 resistance 6.29 6.5 6.68 kΩ
RCFGx_9 Level 9 resistance 8.00 8.3 8.50 kΩ
RCFGx_10 Level 10 resistance 10.18 10.5 10.81 kΩ
RCFGx_11 Level 11 resistance 12.90 13.3 13.70 kΩ
RCFGx_12 Level 12 resistance 15.71 16.2 16.69 kΩ
RCFGx_13 Level 13 resistance 19.88 20.5 21.11 kΩ
RCFGx_14 Level 14 resistance 24.15 24.9 25.65 kΩ
RCFGx_15 Level 15 resistance 29.20 30.1 31.00 kΩ
RCFGx_16 Level 16 resistance 35.40 36.5 38.60 kΩ
SWITCHING FREQUENCY
VRT RT regulation 0.7 0.75 0.8 V
fSW1 Switching frequency RT = 316kΩ 85 100 115 kHz
fSW2 Switching frequency RT = 14kΩ 1980 2200 2420 kHz
tON-MIN Minimum controllable on-time RT = 14kΩ 14 20 50 ns
tOFF-MIN Minimum forced off-time RT = 14kΩ 55 80 105 ns
DMAX1 Maximum duty cycle limit  RT = 316kΩ 98.7% 99.4%
DMAX2 Maximum duty cycle limit  RT = 14kΩ 75% 87%
SYNCHRONIZATION (SYNCIN)
Minimum SYNCIN frequency activity detection Spread Spectrum = off RT = 316kΩ 55 kHz
SYNCIN frequency activity detection vs RT set switching frequency Spread Spectrum = off RT = 14kΩ to 210kΩ –60%
SYNCIN activity detection cycles 3 cycles
fSYNC Syncing frequency range from RT set frequency during synchronization Frequency synchronized to ext. clock min. = 100kHz, max. = 2200kHz –50% 50%
VSYNCIN_H SYNCIN high level input voltage SYNCIN rising 1.19 5.25 V
VSYNCIN_L SYNCIN low level input voltage SYNCIN falling –0.3 0.41 V
ISYNCIN SYNCIN bias current SYNCIN = 3.3V 0.01 1 µA
Minimum SYNCIN pullup / pulldown pulse width 135 ns
VOUT PROGRAMMING (ATRK/DTRK)
VOUT_REG VOUT regulation with ATRK voltage ATRK = 0.2V, VI = 4.5V 5.88 6 6.12 V
ATRK = 0.4V, VI = 10V 11.82 12 12.18 V
ATRK = 0.8V 23.64 24 24.36 V
ATRK = 1.6V 47.28 48 48.72 V
ATRK = 2V 59.10 60 60.90 V
GDTRK Conversion ratio of DTRK duty cycle to VATRK FDTRK = 100kHz, 440kHz 25 mV / %
DTRK duty cycle range 8% 80%
VATRK ATRK voltage for given DTRK duty cycle fDTRK = 100kHz, DC = 8% 0.192 0.2 0.208 V
fDTRK = 100kHz, DC = 40% 0.98 1 1.02 V
fDTRK = 100kHz, DC = 80% 1.98 2 2.02 V
fDTRK = 440kHz, DC = 8% 0.19 0.2 0.21 V
fDTRK = 440kHz, DC = 40% 0.98 1 1.02 V
fDTRK = 440kHz, DC = 80% 1.98 2 2.02 V
VDTRK_H DTRK high level input voltage DTRK rising 1.19 5.25 V
VDTRK_L DTRK low level input voltage DTRK falling –0.3 0.41 V
IATRK Source current when activated through CFG0 19.8 20 20.2 µA
IATRK/DTRK ATRK/DTRK-pin bias current 20µA current is disabled, VATRK/DTRK = 2V 0.01 1 µA
Minimum DTRK pullup / pulldown pulse width 25 ns
SOFT START (SS)
ISS Soft-start current 42.5 50 57.5 µA
VSS-DONE Soft-start done threshold 2.15 2.2 2.25 V
RSS SS pulldown switch RDSON 26 70 Ω
VSS-DIS SS discharge detection threshold 20 45 70 mV
CURRENT SENSE (CSPx, CSNx)
ACS Current sense amplifier gain VCSP = 2.5V 10 V/V
VCLTH Positive peak current limit threshold Referenced to CS input 54 60 66 mV
VNCLTH Negative peak current limit threshold Referenced to CS input, FPWM mode –34 –28 –22 mV
VICL Input current limit Referenced to CS input 65 72 80 mV
ΔVICL_CLTH Delta voltage between ICL and positive peak current threshold 6 12 mV
Peak current limit trip delay 100 ns
VZCD ZCD threshold (CSPx – CSNx) CS input falling, fSW = 100kHz, DEM 0 1.5 5 mV
VZCD_BYP ZCD threshold for phase 1 in bypass mode (CSP1 – CSN1) –4 –2.5 0 mV
ZCD threshold for phase 2 in bypass mode (CSP2 – CSN2) –4 –2.5 0 mV
VSLOPE Peak slope compensation amplitude Referenced to CS input, fSW = 100kHz 40 48 55 mV
ICSNx CSNx current Device in Standby state, VI = VBIAS = VOUT = 12V 1.2 µA
ICSPx CSPx current 150 170 µA
ΔIph1_ph2 Peak Inductor Current unbalance (Phase 1 to Phase 2) VCL = 60mV –10 0 10 %
CURRENT MONITOR / LIMITER WITH DELAY (IMON/ILIM)
GIMON Transconductance Gain 0.283 0.333 0.383 μA/mV
IOFFSET Offset current 3 4 5 μA
VILIM ILIM regulation target 0.93 1 1.07 V
VILIM_th ILIM activation threshold 0.95 1 1.25 V
VILIM_reset DLY reset threshold ILIM falling, referenced to VILIM 85% 88% 91%
IDLY DLY sourcing/sinking current 4 5 6 μA
VDLY_peak_rise VDLY rising 2.45 2.6 2.75 V
VDLY_peak_fall VDLY falling 2.25 2.4 2.55 V
VDLY_valley 0.2 V
ERROR AMPLIFIER (COMP)
Gm Transconductance 700 1000 1300 uS
ACOMP-PWM COMP-to-PWM gain 1 V/V
VCOMP-MAX COMP maximum clamp voltage COMP rising 2.3 2.6 2.9 V
VCOMP-MIN COMP minimum clamp voltage, active in DEM COMP falling 0.38 0.48 0.55 V
COMP minimum clamp voltage, active in FPWM COMP falling 0.13 0.16 0.19 V
VCOMP-offset Offset in respect to min clamp COMP falling 0.01 0.03 0.06 V
ISOURCE-MAX Maximum COMP sourcing current VCOMP = 0V 90 µA
ISINK-MAX Maximum COMP sinking current VCOMP = 2.6V 100 µA
OPERATION MODES
VMODE_H MODE-pin high level FPWM 1.19 5.25 V
VMODE_L MODE-pin low level DEM –0.3 0.41 V
IMODE MODE-pin bias current MODE = 3.3V 0.01 1 µA
OVER / UNDER VOLTAGE MONITOR
VOVP-H Overvoltage threshold VOUT rising (referenced to error amplifier reference) 108% 110% 112%
VOVP-L Overvoltage threshold VOUT falling (referenced to error amplifier reference) 101% 103% 105%
VOVP_max-H Overvoltage threshold 64V VOUT rising (referenced to error amplifier reference) 63 64 65 V
50V 49 50 51 V
35V 34 35 36 V
28.5V 27 28.5 30 V
VOVP_max-L Overvoltage threshold 64V VOUT falling (referenced to error amplifier reference) 62 63 64 V
50V 48 49 50 V
35V 33 34 35 V
28.5V 26 27.5 29 V
VUVP-H Undervoltage threshold VOUT rising (referenced to error amplifier reference) 91% 93% 95%
VUVP-L Undervoltage threshold VOUT falling (referenced to error amplifier reference) 88% 90% 92%
PGOOD
RPGOOD PGOOD pulldown switch RDSON 1mA sinking 90 180 Ω
Minimum BIAS for valid PGOOD 2 V
MOSFET DRIVER (HBx, HOx, SWx, LOx)
High-state on resistance (HO driver) 100mA sinking, HB – SW = 5V 1.1 2 Ω
Low-state on resistance (HO driver) 100mA sourcing, HB – SW = 5V 0.6 1.2 Ω
High-state on resistance (LO driver) 100mA sinking, VCC = 5V 1.1 2 Ω
Low-state on resistance (LO driver) 100mA sourcing, VCC = 5V 0.7 1.4 Ω
VHB-UVLO HB – SW UVLO threshold HB – SW rising 2.85 3.05 3.25 V
VHB-UVLO HB – SW UVLO threshold HB – SW falling 2.6 2.8 3 V
VHB-HYS HB – SW UVLO threshold hysteresis 250 mV
IHB-SLEEP HB quiescent current in bypass HB – SW = 5V 8 15 µA
ICP HB charge pump current available at HBx-pin BIAS = 4.5V, VOUT = 6V 55 75 100 µA
DEAD TIME CONTROL
DT1 HO off to LO on and LO off to HO on dead time Setting 1 7 14 30 ns
DT2 Setting 2 17 30 50 ns
DT3 Setting 3 32 50 75 ns
DT4 Setting 4 50 75 110 ns
DT5 Setting 5  68 100 140 ns
DT6 Setting 6 85 125 180 ns
DT7 Setting 7 105 150 215 ns
DT8 Setting 8 135 200 285 ns
THERMAL SHUTDOWN (TSD)
TTSD-RISING Thermal shutdown threshold Temperature rising 175 °C
TTSD-HYS Thermal shutdown hysteresis 15 °C
TIMINGS
STANDBYtimer STANDBY timer 130 150 170 µs