SNVSCT1A October 2025 ā December 2025 LM5066H
PRODUCTION DATA
ADC_CONFIG_2 is a manufacturer-specific command for configuring or reading parameter selection and decimation rate (sample skip count) for high speed ADC sample buffering as described in READ_SAMPLE_BUF (C9h, Block Read).
This command uses the PMBus read or write byte protocol.
The details of this register are shown in ADC_CONFIG_2 Register Description.
| Bit | Name |
Value |
Description |
Default |
|---|---|---|---|---|
|
7 |
Reserved |
0 |
Reserved |
0 |
| 6 | ADC Full Scale | 1 | ADC Full scale is 2xVCL | 0 |
| 0 | ADC Full scale is 1xVCL | |||
|
5:3 |
BUF_CH_SEL |
Parameter selection for buffering | ||
|
111 |
Reserved (Will default to IIN) |
000 |
||
|
110 |
||||
|
101 |
||||
|
100 |
VAUX |
|||
|
011 |
VTEMP |
|||
|
010 |
IIN |
|||
|
001 |
VOUT |
|||
|
000 |
VIN | |||
|
2:0 |
DEC_RATE |
Decimation rate (sample skip count) for ADC sample buffering |
||
|
111 |
Decimation rate (sample skip count) = 7 |
0000 |
||
|
110 |
Decimation rate (sample skip count) = 6 |
|||
|
101 |
Decimation rate (sample skip count) = 5 |
|||
|
100 |
Decimation rate (sample skip count) = 4 |
|||
|
011 |
Decimation rate (sample skip count) = 3 |
|||
|
010 |
Decimation rate (sample skip count) = 2 |
|||
|
001 |
Decimation rate (sample skip count) = 1 |
|||
|
000 |
Decimation rate (sample skip count) = 0 |