3.3 Interrupt Based Encoding and Decoding

With SFO calibration is being implemented in the background, the encoding routine is implemented in the foreground at the transmitter using an interrupt-based mechanism. The showcasing example utilizes internal ADC for sampling the external signal at a specified sampling frequency, the completion of ADC conversion triggers an ISR, which then calls the encoding function. The encoding function calculates the normalized digital data based on the user-configured bit resolution. This normalized value is then mapped to the duty of PWM signal. For example values, see Figure 5. It is important to note that the HRCAP module has constraints in terms of minimum pulse width of captured signal. For more details, see the TMS320F28004x Piccolo™ Microcontrollers Data Sheet. In order to satisfy this constraint, the encoded duty values are mapped linearly in range of 10% - 90% (the smallest data value will be mapped to 10% duty and the maximum to 90%). Also, the auto-conversion feature, discussed in the TMS320F2838x Microcontrollers Technical Reference Manual, supported by the HRPWM module allows to update the fractional duty value of signal in just single register write. The MEP calibration module uses the values in the HRMSTEP and CMPAHR registers to automatically calculate the appropriate number of MEP steps represented by the fractional duty cycle and move the high-resolution PWM signal edge accordingly. For more information, see the TMS320F2838x Microcontrollers Technical Reference Manual. This differentiated feature saves critical CPU cycles and improves the encoding latency. The encoding routine snippet is shown below:

// // Function for updating HRPWM duty // void configDuty (void) { // // Calculating normalized digital value and then calculating duty in // floating point format based on the normalized value. Then writing the // fixed point converted version of duty value to the CMPA register as // automatic conversion mode of HRPWM is used // dig_value_input_norm = dig_value_input * ADC_NORM; duty = 0.1f + dig_value_input_norm * 0.8f; HWREG(EPWM1_BASE + HRPWM_O_CMPA) = (uint32_t) ((duty* (float32_t)time_period) *(float_t) ((uint_32) 1 << 16) + 0.5f); }

The decoding routine at the receiver is also implemented using an interrupt-based mechanism. As per the discussed capture sequence in Section 2.2, the second rising edge of transmission signal triggers an ISR where the duty ratio of the relative count values is computed. The constant offset is subtracted from the duty value and then the normalized data value is decoded based on the linear mapping equation. This normalized value is then scaled as per the user-configured bit resolution (see Figure 6). TMU/FPU based intrinsics are used for division/modulo operations in order to accelerate the decoding routine and minimize the latency. The decoding sequence is shown below:

// // Calculating duty value_comp // duty_output = __divf32 ((float32_t)absCountOn1, (float32_t) absCountPeriod1); // // Removing constant offset // duty_output_minus_offset = duty_output - duty_offset; // // Decoding normalized output (i.e. between 0 and 1) using duty value_comp // For duty value, 'x', the decoded normalized output will begin // (x-0.1)/0.8 i.e. (x-1)*1.25 // duty_output_norm = (duty_output_minus_offset - 0.1f) * 1.25f; // // Scaling the normalized output with the desired bit resolution // duty_value_output = (uint16_t) (dig_value_output_norm * (uint16_t)(1 < < BIT_RESOLUTION) + 0.5f);