SPRACO5 September   2019 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DK-Q1

 

  1.   Leveraging High Resolution Capture (HRCAP) for Single Wire Data Transfer
    1.     Trademarks
    2. 1 Introduction
    3. 2 System Showcase
      1. 2.1 HRPWM: Encoding Unit
      2. 2.2 HRCAP: Decoding Unit
    4. 3 Software Flow
      1. 3.1 User Configurable Parameters
      2. 3.2 SFO Background Loop
      3. 3.3 Interrupt Based Encoding and Decoding
      4. 3.4 Offset Calibration
    5. 4 Experimental Setup and Results
    6. 5 Summary
    7. 6 References

User Configurable Parameters

The example supports the following user configurable parameters to let customers quickly adopt this technique based on their design requirements:

  • BIT_RESOLUTION: The resolution at which you want to encode/decode data. To choose the appropriate resolution based on the ENOB and latency requirements, see Table 1. For a particular PWM transmission frequency, the ENOB value specified in Table 1 suggests that particular number of bits of data can be transferred accurately and reliably using this technique. If a higher resolution than ENOB is chosen, then the least significant (BIT_RESOLUTION - ENOB) bits could fluctuate. By default, resolution is set to 11-bit in the given examples.
  • ADC_NORM: Based on selected BIT_RESOLUTION, you need to compute the scale factor as (1 / 2^ (BIT_RESOLUTION)) and program this value. This scale factor is actually going to be used for encoding, thus, do not forget to update this value along with BIT_RESOLUTION.
  • PWMCLK: The EPWM module clock at which you want to operate, choose either 100 MHz/200 Mhz depending upon maximum supported by the particular transmitter device. For example, F2838x can support the 200 MHz module clock while F28004x can support the maximum up to 100 MHz. By default, it is set to 100 MHz in transmitter code.
  • PWM_FREQ: The PWM signal frequency used for transmission. To choose the appropriate PWM transmission frequency based on ENOB and latency requirements, see Table 1. By default, it is set to 200 KHz in the example.
  • ADC_SAMPLE_FREQ: The ADC trigger frequency in KHz, by default its set to 25 KHz. The maximum programmable value of ADC_SAMPLE_FREQ can be equal to PWM_FREQ.
  • USE_ADC_INPUT: Control switch used to choose between manual user-written data or ADC acquired data. By default, it is set to 0 (manual mode).