SPRACU8B August   2021  – January 2023 AM68 , AM68 , AM68A , AM68A , AM69 , AM69 , AM69A , AM69A , DRA821U , DRA821U , DRA829V , DRA829V , TDA4VM , TDA4VM

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
      1. 1.1.1 Supported Features (version 0.10.0)
      2. 1.1.2 Unsupported Features (version 0.10.0)
    2. 1.2 Spreadsheet Overview
      1. 1.2.1 Input Worksheets
      2. 1.2.2 Output Worksheets
      3. 1.2.3 Other Worksheets
    3. 1.3 Default SDK Configurations
  4. 2Customizing DDR Configuration
    1. 2.1 Config Worksheet
      1. 2.1.1 System Configuration
      2. 2.1.2 Memory Burst Configuration
    2. 2.2 DRAMTiming Worksheet
      1. 2.2.1 Latency Parameters
      2. 2.2.2 Non-Latency Parameters
    3. 2.3 IO Control Worksheet
      1. 2.3.1 Determining IO Settings
      2. 2.3.2 Processor/DDR Controller IO
      3. 2.3.3 DRAM I/O
  5. 3Software Considerations
    1. 3.1 Updating U-Boot
      1. 3.1.1 Updating DDR Register Settings
      2. 3.1.2 Updating Source to Set Available Memory Size
    2. 3.2 Updating RTOS PDK
      1. 3.2.1 Updating DDR Register Settings
  6. 4Troubleshoot Guide
    1. 4.1 Topics/Issues
      1. 4.1.1 Topic 1
      2. 4.1.2 Topic 2
      3. 4.1.3 Topic 3
  7. 5References
  8.   Revision History

1.1.1 Supported Features (version 0.10.0)

  • DDR interface of following TI processor part numbers: DRA821x, DRA829x, TDA4AH, TDA4AL, TDA4AP, TDA4VE, TDA4VH, TDA4VL, TDA4VM, TDA4VP
  • DDR Memory Types: LPDDR4
  • DDR Bus Width: 32 bits or 16 bits
  • Single or dual rank LPDDR4 memories
  • Customization of IO drive strength / termination
  • Configurable DDR timing parameters
  • Enable the DDRSS hardware training algorithms during DRAM initialization, including:
    • IO calibration of the controller/PHY
    • Command bus training, including the reference voltage programmed in MR12 of the DRAM
    • Write leveling
    • Read DQS gate training
    • Read data eye (DQ) training, including the reference voltage of the controller / PHY
    • Write data eye (DQ) training, including the reference voltage programmed in MR14 of the DRAM
  • Enablement of the following DDRSS hardware periodic training algorithms during normal operation:
    • Write data eye (DQ) training, excluding the reference voltage
    • ZQ Calibration
  • Non-power-of-2 LPDDR4 densities (example: 3Gb, 6Gb, 12Gb)
  • Data bus inversion